"Collaboration framework and context3D integration technology (i.e. stacking chips vertically) has become a product differentiator to be competitive in the market place by delivering better performance with smaller footprint at a cost-effective way. It integrates multiple functional components into one device thus reducing development effort of product manufacturers and enabling faster time-to-market. As more components are stacked together and planar features decrease at the same time, 3D integration technology brings many new challenges for electrical fault isolation and failure analysis. Defect localization accuracy has become increasingly challenging because the defect is now deeply buried inside the package, and it becomes more difficult for the conventional fault isolation tools to ""see"" them. These challenges require more capable fault isolation tools and techniques with better accuracy, resolution and sensitivity. Lock-in thermography (LIT) is a powerful, non-contact and non-destructive technique that has been successfully applied for electrical fault isolation of 2D packages. Yet its success in 3D packages has been limited because of its vertical/Z accuracy, extensive data collection and in-consistent results as reported by many studies. Work description· Literature review· Training on the THEMOS-1000 (Hamamatsu) thermal emission microscope: 2-D failure localization· Assessment of the depth measurement feature installed on the tool (measurement, simulation…)· Writing of a report with pros/cons, relevance of the technique w or w/o layout information… Host institutionThis internship will take place in the LCFC lab (Laboratoire de Caractérisation et de Fiabilité des Composants, Characterization and Reliability lab.) in a technological and scientific research environment. A specialization in heat science will be a plus for the success of the internship."