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Current
Projects
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- ANR,
NV-APROC Project: "
Non Volatile MRAM-based Asynchronous PROCessor", 2019 - 2023
--> Coordinator of the project.
--> Involved in full custom and digital non-volatile IP design.
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- ANR,
MISTRAL Project: "
MRAM/CMOS Hybridization to Secure Cryptographic Algorithms", 2019 - 2023
--> Involved as scietific responsible for Spintec, project management.
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- CNRS 80|PRIME,
CARMEM Project: "
Modèles de Caractérisation par Apprentissage pour la Qualité des Technologies de Mémoires Émergentes, 2021 - 2024.
--> Involved as expert in integrated circuit design.
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SPINBRAIN: "
Spintronic-based Neural Network", 2020 - 2022
--> Involved as expert in integrated circuit design.
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HANS: "
Design of hybrid CMOS/magnetic hardware accelerators for machine learning applications", 2019 - 2022
--> Involved as expert in integrated circuit design.
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Former
Projects
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- ANR,
ELECSPIN Project: "
ELECtric field assisted SPINtronic devices, 2016 - 2020. [url]
--> Involved as expert in integrated circuit design.
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- H2020-ICT,
GREAT Project: "
heteroGeneous integRated magnetic tEchnology using multifunctional
standardized sTack (MSS)", 2016 - 2019. [url]
--> Involved in specific design, i.e. non-volatile logic and/or
STT-MRAM based memory.
--> In charge of non-volatile IC tests.
--> Hybrid MRAM/CMOS Process Design Kit development.
--> CMOS / Post-process interface expert.
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- Internal
CEA project, MAD Project:
"Design and demonstration of digital IP based on emerging non-volatile MEMories ", 2014 - 2018.
--> Characterisation block design and test, CMOS/STT-MRAM
integration interface and managment.
--> Engineer and post-doc supervisor.
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- ANR,
MASTA Project: "
MRAM-based design, test and reliability for ultra low power SoC, 2016 -
2019. [url]
--> Involved in digital micro processor and micro controler
architectures and evaluations.
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- ERC
Advanced Grant, HYMAGINE Project: "
Hybrid CMOS/Magnetic components and systems for energy efficient, non-volatile,
reprogrammable integrated electronics ", 2010 - 2015. [url]
--> Project managment, CMOS/STT-MRAM process integration
managment, foundry interface, MTJ characterization, ASIC design and
test.
--> Engineer and post-doc supervisor.
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- European
Commission FP7, SPOT Project: " Spin
Orbit Torque memory for cache & multicore processor
applications", 2012 - 2015. [url]
--> Work Package leader: modelling, ASIC demonstrator managment,
logic and SOT-based MRAM design, wafer characterization, demonstrator
test and characterization.
--> Post-doc supervisor.
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- CEA
- Nanosciences, NOVELASIC Project:
" NOn VolatilE Logical ASynchronous Integrated Circuit ", 2015.
--> Coordinator of the project.
--> Post-docs supervisor.
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- ANR-P2N,
DIPMEM Project:
"Design and demonstration of digital IP based on emerging non-volatile MEMories ", 2012 - 2015. [url]
--> STT-MRAM characterisation block design and test,
CMOS/STT-MRAM integration interface and managment.
--> Engineer and post-doc supervisor.
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- ANR-P2N,
MARS Project: "
MRAM based Architecture for Reliable and low power Systems ", 2012 -
2015. [url]
--> Involved in STT-MRAM-based non-volatile processor
architecture studies.
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