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RISC-V Summit Europe: CEA will participate !

Du 05/06/2023 au 09/06/2023
Barcelona, Spain

« The RISC-V Summit Europe will be the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation on RISC-V. »​​​​

CEA and IRT booths locations are 19 & 20  
CEA will have the 10min talk on Tuesday 13:15 CET – By Mikael CARMONA​

As a gold sponsor, CEA will be present with a booth. Please come to discuss with our experts and to discover our latest technological innovations:


VASCO 2, an ASIC to highlight the latest innovations in security of component"

What about : “ VASCO 2 (ASIC Vehicle for Component Security) integrates innovative, patented hardware security building blocks on 22 nm FD-SOI silicon. It enables all types of standard or customized tests to validate these technologies in operational conditions in order to characterize innovative security blocks and to prepare a transfer to industry.

VASCO 2 highlights the relevance and characteristics of these hardware IPs for industry by matching current challenges in hardware security: securing processors, securing and accelerating pre- and post-quantum cryptography, modelization and characterization of True Random Number Generators (TRNG), securing memories, etc. With VASCO 2, manufacturers have access to comprehensive data on hardware security IP: security level, power consumption, silicon surface area, and impact on cycle time."


*VXP Extended Precision Processor: The "VXP" is an extended precision computing accelerator developed by CEA-List that speeds up scientific computing by a factor typically ranging from 3 to 10 or even more.

For more information : VXP Extended precision Processor (cea.fr)


*SESAM : Explore, simulate, and validate complex electronic architectures

SESAM is a digital architecture design environment used to speed up design space exploration (DSE) through simulation and rapid validation. Users can model a complex memory hierarchy and estimate its performance, for example, thanks to a wide variety of available processor and device models.

For more information : SESAM (cea.fr) 

*HybroGen Compilation hybride: The transfer of data between a processor and its memory accounts for 80% of the energy used in computing operations. The downside is that today's programming languages are not compatible with these innovative architectures. […] The HybroGen compiler represents a break away from 70 years of programming by translating the programmer's instructions into code that can be executed on these new architectures. The researchers tested HybroGen, using it to program applications on the new architectures.

For more information : July 7, 2021 | In-memory computing could help improve circuit performance (cea.fr)


As a silver sponsor, IRT Nanoelec will be also present with a booth and it will be possible to have information about SCRAMBLE CACHE technology.

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