L-UTSOI MODEL DEFINITIONS
L-UTSOI is a compact model dedicated to Fully-Depleted on Silicon-On-Insulator (FDSOI) technologies with low doped channel, developed at CEA-LETI and previously named Leti-UTSOI.
The model structure is the same as in the different versions of Leti-UTSOI1 and, thus, similar to PSP. It is based on a hierarchical construction featuring two levels of parameter set:
-A local mode, in which the knowledge of the device geometry (channel length and width) is not needed. In this mode, the local parameter values are directly obtained from the model cards.
-A global mode, in which the local parameters are computed from the global model card and the device geometry through scaling laws. The so-computed local parameters are then used to compute the model equations. In this mode, some local parameters can also be modified according to the stress model.
"Surface potential based model of ultra-thin fully depleted SOI MOSFET for IC simulations", O. Rozeau, M. A. Jaud, T. Poiroux and M. Benosman, in IEEE International SOI Conference, 2011.https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6081682"Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part I: Interface Potentials Analytical Model", T. Poiroux, Member, IEEE, O. Rozeau, P. Scheer, S. Martinie, M. A. Jaud, M. Minondo, A. Juge, J. C. Barbé, and M. Vinet. IEEE Transactions on Electron Devices ( Volume: 62 , Issue: 9 , Sept. 2015 )https://ieeexplore.ieee.org/abstract/document/7185387"Leti-UTSOI2.1: A Compact Model for UTBB-FDSOI Technologies—Part II: DC and AC Model Description", Thierry Poiroux, Member, IEEE, O. Rozeau, Patrick Scheer, Sébastien Martinie, Marie-Anne Jaud, M. Minondo, André Juge, J. C. Barbé, and Maud Vinet. IEEE Transactions on Electron Devices ( Volume: 62 , Issue: 9 , Sept. 2015 )https://ieeexplore.ieee.org/abstract/document/7185413"UTSOI2: A complete physical compact model for UTBB and independent double gate MOSFETs", T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, S. Puget, M.A. Jaud, S. El Ghouli, J.C. Barbé, A. Juge, O. Faynot. 2013 IEEE International Electron Devices Meeting.https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6724616Presentation @ MOS-AK Grenoble 2015http://www.mos-ak.org/grenoble_2015/presentations/T10_Poiroux_MOS-AK_Grenoble_2015.pdfPresentation @ MOS-AK WashingtonDC 2013http://www.mos-ak.org/washington_dc_2013/presentations/T9_Poiroux_MOS-AK_WashingtonDC_2013.pdf
CEA-LETI supports releases of compact models in the form of Verilog-A(MS) Source Code.
Verilog-A Language Reference Manual 2.2 is published in 2004 by Accellera.
An implementation in Verilog-A of each of the supported model levels, can be found at the corresponding Releases pages.
CEA is a French government-funded technological research organisation in four main areas: low-carbon energies, defense and security, information technologies and health technologies. A prominent player in the European Research Area, it is involved in setting up collaborative projects with many partners around the world.