You are here : Home > Extraction, Testing & Bugs > Extraction, Testing & Bugs

Extraction, Testing & Bugs

Published on 30 June 2021


To make a compact transistor model represent an actual, individual transistor, one needs to assign appropriate values to the parameters of the compact model. Parameter extraction is the procedure for obtaining an appropriate set of values for the parameters for any given transistor.


All L-UTSOI model parameters can be extracted in a step-by-step procedure from measured data. Strategies for extraction of parameter values can be found in the L-UTSOI documentation page.


Verification of  L-UTSOI is supported on basis of the Q&A toolkit of the Compact Mode​ling Coalition (CMC). With  L-UTSOI releases we post the variant of this toolkit that is run at CEA-Leti to verify the  L-UTSOI model. In the subdirectory  L-UTSOI/ of this toolkit one can find tests and reference data to support  L-UTSOI model verification.

The purpose of the tests is to support conformance checking between various implementations. Tests have been carefully developed to focus on physically relevant parts of the transistor characteristics and avoid extremely low- or extremely high bias regimes, where the output of simulations is known to be simulator dependent. Large bias steps and extreme initial conditions have been avoided, so as to avoid appealing strongly to the convergency aids of numerical solvers involved. Robustness testing is explicitly not within the focus of this test suite.


With the various  L-UTSOI releases we deliver the variant of the CMC Q&A toolkit that is run at CEA-Leti to verify L-UTSOI model implementations. In turn, in the current version of the CMC Q&A toolkit, we keep support of past versions of the  L-UTSOI model, as well as the Verilog-A implementations of these.​


To deal with (presumed) bugs in the current release we follow the procedures as outlined in the 
CMC Bug Reporting Procedure for Standard Models.