Vous êtes ici : Accueil > L'institut > Fundamentals of ultrascaled 3D magnetic tunnel junctions and integration routes for high density memory arrays


Soutenance de thèse

Fundamentals of ultrascaled 3D magnetic tunnel junctions and integration routes for high density memory arrays

Vendredi 13 octobre 2023 à 14:00, salle de séminaires 445, bâtiment 10.05 du CEA-Grenoble 

Publié le 13 octobre 2023
Spintronique et Technologie des Composants, Institut de Recherche Interdisciplinaire de Grenoble
The perpendicular Spin Transfer Torque Magnetic Random Access Memory (p-STT-MRAM) is one of the most promising emerging non-volatile memory technologies. As these devices are limited by their thermal stability factor at technological nodes smaller than 20 nm, their downsize capability is compromised. A possible solution to this limitation relies in taking advantage of the shape anisotropy, by increasing substantially the thickness of the storage layer. Thanks to this now vertical aspect-ratio, the stability can be enhanced significantly to sub-10 nm nodes and this new memory element is named Perpendicular Shape Anisotropy MTJ (PSA-MTJ). Although a promising path to dense MTJ arrays, there are still several challenges that need to be addressed before adopting this technology. In this dissertation we address the bottlenecks of this novel memory element, namely the fabrication process and improvement of the reversal mechanism. Making use of micromagnetic simulations it is shown the different reversal mechanisms of the PSA-MTJ and a study on how to avoid a non-coherent reversal while keeping fast switching times at low switching voltages is realised. It is namely shown that it is necessary to finely tune the aspect-ratio of the memory cell to achieve faster switching times. This increase in switching speed comes, not only from the increase in anisotropy field (in a macrospin approximation, it increases to maintain the same stability at proportionally smaller magnetic volume), but also due to the stronger effect of the spin-transfer-torque. This idea is used as a baseline for fabricated sub-10 nm elements with vertical aspect-ratio, where switching is achieved through spin-transfer-torque. Usual p-MTJs are also fabricated using the same methodology and it is shown an increase in figure of merit (∆/Ic0) (a known parameter that relates the ratio between the stability and the critical current necessary to switch the device) as the diameter is reduced. In the limit of the dimension, devices as small as 5 nm in diameter show a stochastic behaviour (direction of magnetization fluctuates with the thermal noise), well controlled by the STT current. This opens the path to dense arrays of stochastic MTJs with ultra-small diameter and small switching current. However, to fabricate a dense MTJ array there are still several challenges that need to be solved, namely the stray field from neighbouring bits but also the shadow effect, which limits the pitch between devices. To tackle these constraints we make use of electrodeposition in pre-patterned nano-vias, either by electro-beam lithography (EBL) or direct self-assembly (DSA), to fabricate ultra-small MTJ. The nano-vias created by EBL show potential to achieve sub-10 nm thanks to the already small pre-defined diameter but also thanks to a more uniform ion beam etching of the pillar, avoiding tilted or fallen devices. STT-switching and very large TMR values were shown in single devices measurements using this approach for conventional pMTJ. The nano-vias created by DSA show promise for very small pitch (≈ 50 nm) and small node (≈ 25 nm) MTJ arrays. These can be adapted for CMOS integration, as the nano-via can be filled directly on top the already existing W via. A process flow that makes use of a common bottom electrode was devised and structural and magnetic characterization of the nano-vias was realised. A solution to the strong cross talk between magnetic devices was demonstrated analytically and micromagnetically through the use of a core-shell system for the storage layer. Thanks to the vertical aspect ratio of the magnetic layer, this system adds stability and reduced switching time without a penalty in the switching voltage. Additionally, the system can be adjusted so that there is no remnant stray field inside a magnetic array.

Plus d'information :https://www.spintec.fr/phd-defense-fundamentals-of-ultrascaled-3d-magnetic-tunnel-junctions-and-integration-routes-for-high-density-memory-array/

L'accès à la salle 445 nécessite un laisser passer. Merci de contacter admin.spintec@cea.fr avant le 06 octobre.