The explosive growth of data and sub-10 nm transistor scaling have driven up chip power, making it attractive to bring non-volatile memory closer to the CPU. Magnetic random-access memory (MRAM), based on magnetic tunnel junctions, is a leading contender. While STT-MRAM is already in production, spin–orbit torque MRAM (SOT-MRAM), based on spin currents from the spin Hall and Rashba effects, offers faster sub-nanosecond switching and superior endurance.
A key challenge, however, is deterministic switching. Even with external fields, write probability can collapse at high currents due to intrinsic backswitching. We systematically investigate this phenomenon in sub-100 nm CoFeB pillars on β-W using statistical measurements and macrospin simulations that reproduce experiments. The results suggest practical mitigation strategies, including free layers with high damping, interface engineering to tune the field-like/damping-like torque balance, and tailored pulse shapes.
To eliminate the external-field requirement, we examine combined SOT and STT writing. While this boosts practicality, it introduces reliability concerns linked to reference-layer imperfections. Through write error rate (WER) experiments and improved stack, we identify optimal pulsing strategies and demonstrate low WER at sub-critical currents. We also disentangle contributions from stray fields, VCMA, STT, and Joule heating, and highlight the fundamental difference in symmetry-breaking mechanisms of external field and STT.
Finally, we explore orbital torques in Co/Pt/Ta trilayers, revealing a damping-like torque efficiency more than twice that of Co/Pt, which increases with temperature, alongside a sizable field-like component. By decoupling spin and orbital contributions, we uncover their relaxation mechanisms. These results highlight new pathways toward robust, deterministic, and energy-efficient SOT-MRAM.

Plus d'information :https://www.spintec.fr/phd-defense-by-kuldeep-ray-development-of-sot-mram-technology-for-integration-in-functional-devices/
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