vertical heterojunction ge0.92sn0.08/ge gate-all-around nanowire pmosfets
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| Date | 2019 |
| Date | |
| Auteurs | Liu,- M | Mertens,- K | von den driesch,- N | Grap,- T | Trellenkamp,- S | Hartmann,- J-m | Knoch,- J | Buca,- D | Zhao,- Q-t | |
| Source | 2018 IEEE Global Conference on Signal and Information Processing, GlobalSIP 2018 | 33rd Conference on Design of Circuits and Integrated Systems, DCIS 2018 | |
| Résumé | Vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top-down approach are reported. With optimized processes, pFETs with nanowire diameters as small as 40 nm were achieved and a decent ION/IoFFratio of 4×104 was obtained due to the GAA nanowire geometry and the GeSn/Ge heterostructure. Devices with larger nanowire diameters exhibited higher ION, ION/IOFF ratio and transconductance. Similar subthreshold swing (SS) characteristics were present in pFETs with various nanowire diameters considering the compensating effect between top source resistance and gate electrostatics induced by nanowire diameter. © 2019 IEEE. |
| DOI | http://dx.doi.org/10.1109/EUROSOI-ULIS45800.2019.9041910 |
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