ultraviolet nanosecond laser annealing for low temperature 3d-sequential integration gate stack
| Description | |
| Date | 2019 |
| Date | |
| Auteurs | Kerdilès,- S | Acosta-alba,- P | Royet,- A-s | Lassarre,- J | Perrot,- C | Aussenac,- F | Brunei,- L | Fenouillet-béranger,- C | |
| Source | Gallium Nitride and Silicon Carbide Power Technologies 7 - 232nd ECS Meeting | |
| Résumé | For the top tier in a 3D sequential integration, we propose a low temperature gate first approach in which an in-situ doped amorphous silicon layer is deposited at 475°C then subsequently converted into a polycrystalline film using ultraviolet nanosecond laser annealing. We demonstrate the ability to obtain a low resistance poly-Si gate for the top transistors within a thermal budget expected to preserve the bottom devices electrical performance. © The Electrochemical Society. |
| DOI | http://dx.doi.org/10.1149/09301.00l9ecst |
| Type de documents | |
| Impact Factor | |