Impact of strain on access resistance in planar and nanowire CMOS devices
| Auteurs | Berthelon R., Andneu F., Triozon F., Casse M., Bourdet L., Ghibaudo G., Rideau D., Niquet Y.M., Barraud S., Nguyen P., Le Royer C., Lacord J., Tabone C., Rozeau O., Dutartre D., Claverie A., Josse E., Arnaud F., Vinet M. |
| Year | 2017-0371 |
| Source-Title | Digest of Technical Papers - Symposium on VLSI Technology |
| Affiliations | CEA-LETI, France, STMicroelectronics, France, CEMES and, France, IMEP-LaHC, France |
| Abstract | We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (RACC) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on Racc (-21% for 4 V Vb and -53% for -1GPa stress on pMOS FDSOI). This is in agreement with Non-Equilibrium-Green-Functions (NEGF) simulations. This RAcc(strain) dependence has been introduced into SPICE, leading to +6% increase of the RO frequency under ?n/p=0.8%/-0.5% strain, compared to the state-of-the-art model. It is thus mandatory for predictive benchmarking and optimized IC designs. © 2017 JSAP. |
| Author-Keywords | |
| Index-Keywords | CMOS integrated circuits, Nanowires, Silicon alloys, VLSI circuits, Access resistance, CMOS devices, Extraction procedure, Non-equilibrium green functions, Novel access, SiGe channels, SiGe source/drain, State of the art, Si-Ge alloys |
| ISSN | 7431562 |
| Lien vers article | Link |