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Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells

Publié le 29 mars 2018
Transistor Temperature Deviation Analysis in Monolithic 3D Standard Cells
Brocard M., Mathieu B., Colonna J.-P., Santos C., Fenouillet-Beranger C., Cao-Minh V.L., Cibrario G., Brunet L., Batude P., Andrieu F., Thuries S., Billoint O.
Source-TitleProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
Univ. Grenoble Alpes, Grenoble, France, CEA, LETI, MINATEC Campus, Grenoble, France
This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient thermal analysis at transistor level. A representative 3D standard cell in 14nm FDSOI technology is considered, using intermediate Back-End-Of-Line (iBEOL) and top tier BEOL. Steady-state and transient power dissipations in NMOS and PMOS are extracted from SPICE simulations with variables such as output load capacitance and operating temperature. 3D thermal simulations are then performed to assess the impact of design parameters such as routing densities, thicknesses of iBEOL and BEOL, their number of metal layers and packaging techniques. Steady-state and transient thermal simulations enable precise analysis to correlate temperature deviation of transistors with these parameters. Design guidelines are provided to limit the temperature deviation between top and bottom tier which can reach 7°Celsius during circuit operations in the worst case. © 2017 IEEE.
3D monolithic integration, 3D VLSI, standard cells, thermal simulation, transient state, transistor level
Cells, Cytology, Integrated circuit manufacture, Thermoanalysis, VLSI circuits, 3-D VLSI, Monolithic integration, Standard cell, Thermal simulations, Transient state, Transistor level, Transistors
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