High Throughput FPGA Implementation for regular Non-Surjective Finite Alphabet Iterative Decoders
| Auteurs | Nguyen-Ly T.T., Savin V., Popon X., Declercq D. |
| Year | 2017-0317 |
| Source-Title | 2017 IEEE International Conference on Communications Workshops, ICC Workshops 2017 |
| Affiliations | CEA-LETI, MINATEC Campus, Grenoble, France, ETIS, ENSEA, CNRS UMR-8051, University of Cergy-Pontoise, France |
| Abstract | This paper deals with the recently introduced class of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs). First, optimization results for an extended class of regular NS-FAIDs are presented. They reveal different possible trade-offs between decoding performance and hardware implementation efficiency. To validate the promises of optimized NS-FAIDs in terms of hardware implementation benefits, we propose two high-throughput hardware architectures, integrating NS-FAIDs decoding kernels. Implementation results show that NS-FAIDs allow significant improvements in terms of both throughput and hardware resources consumption, as compared to a baseline Min-Sum decoder, with even better or only slightly degraded decoding performance. © 2017 IEEE. |
| Author-Keywords | |
| Index-Keywords | Field programmable gate arrays (FPGA), Throughput, Decoding performance, Finite alphabet, FPGA implementations, Hardware architecture, Hardware implementations, Hardware resources, High throughput, Iterative decoder, Hardware |
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