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First SOI Tunnel FETs with low-temperature process

Publié le 29 mars 2018
First SOI Tunnel FETs with low-temperature process
Diaz Llorente C., Le Royer C., Lu C.-M.V., Batude P., Fenouillet-Beranger C., Martinie S., Allain F., Vinet M., Cristoloveanu S., Ghibaudo G.
Source-TitleJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
CEA, LETI, MINATEC Campus, 17 rue des Martyrs, Grenoble Cedex 9, France, IMEP-LAHC, INP-Grenoble, MINATEC Campus, Grenoble, France
We demonstrate for the first time the fabrication and electrical characterization of planar SOI Tunnel FETs (TFETs) with low temperature (LT) processes devoted to 3D sequential integration. The electrical behavior of these TFETs, with junctions obtained by Solid Phase Epitaxy Regrowth (SPER), is analyzed and compared to reference samples (regular process at high temperature, HT). The threshold voltage (VTH) of p-mode operating TFETs shows a 300 mV reduction with similar ON state currents (wrt HT reference), opening path towards optimized devices (very low VTH &, supply voltage VDD) © 2017 IEEE.
3D sequential integration, BTBT, CoolCube, low temperature, SPER, TFET, Tunnel FET, tunneling
Electron tunneling, Field effect transistors, Integration, Threshold voltage, BTBT, CoolCube, Low temperatures, SPER, TFET, Tunnel FET, Temperature
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