Study of forming impact on 4Kbit RRAM array performances and reliability
| Auteurs | Nguyen C., Cagli C., Molas G., Sklenard B., Nail C., Hajjam K.E., Nodin J.F., Charpin C., Bernasconi S., Reimbold G. |
| Year | 2017-0275 |
| Source-Title | 2017 IEEE 9th International Memory Workshop, IMW 2017 |
| Affiliations | CEA, LETI, MINATEC Campus, Grenoble, France |
| Abstract | We present a novel study on the impact of the forming stage on RRAM reliability on multi-Kbit array. First we show how the forming stage dictates the CF radius and impacts on the Vset distribution even after long cycling. Then we show how the low frequency noise, and in particular the Random Telegraph Noise (RTN), is directly linked to the forming stage. We find that as the forming current decreases, even if a smaller level number in RTN appears, it creates a larger pick-To-pick noise. This is demonstrated to negatively impact on the Roff distribution reading and then on resistance window during subsequent cycling. We explain this effect thanks to a semi-Analytic model, validated with ab-initio calculations. Low current forming, although beneficial for retention [1] is however found to be detrimental for window margin. © 2017 IEEE. |
| Author-Keywords | |
| Index-Keywords | RRAM, Ab initio calculations, Analytic modeling, Array performance, Low currents, Low-Frequency Noise, On-resistance, Random telegraph noise, Random access storage |
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| Lien vers article | Link |