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Reliability compact modeling approach for layout dependent effects in advanced CMOS nodes

Publié le 29 mars 2018
Reliability compact modeling approach for layout dependent effects in advanced CMOS nodes
Auteurs
Ndiaye C., Berthelon R., Huard V., Bravaix A., Diouf C., Andrieu F., Ortolland S., Rafik M., Lajmi R., Federspiel X., Cacho F.
Year2017-0256
Source-TitleIEEE International Reliability Physics Symposium Proceedings
Affiliations
REER/STMicroelectronics, 850 rue Jean Monnet, Crolles, France, ISEN REER-IM2NP UMR CNRS 7334, Pl. G. Pompidou, Toulon, France, CEA-LETI, Minatec Campus, 17 rue des Martyrs, Grenoble Cedex 4, France
Abstract
In this paper, we have analysed and modelled the layout dependent effects (LDE) found in pMOSFET transistors from 14nm UTBB FDSOI CMOS technology. Experiments show that changing the layout has a clear impact on threshold Voltage (Vth), under NBTI reliability and on Ring Oscillator (RO) Frequency drift. Compact models taking account the impact of LDE on Vth, NBTI reliability, and on RO frequency are proposed. Measurement data are fitted with a new compact model showing that the obtained results are in very good agreements with the modelling. © 2017 IEEE.
Author-Keywords
CMOS performance, compressive strain, FDSOI, Layout effects, NBTI damage
Index-Keywords
CMOS integrated circuits, Reliability, CMOS technology, Compressive strain, FDSOI, Frequency drifts, Layout dependents, Layout effects, Measurement data, Ring oscillator, Integrated circuit layout
ISSN15417026
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