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Tunnel FET based refresh-free-DRAM

Publié le 29 mars 2018
Tunnel FET based refresh-free-DRAM
Auteurs
Gupta N., Makosiej A., Vladimirescu A., Amara A., Anghel C.
Year2017-0230
Source-TitleProceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
Affiliations
MINARC Laboratory, Institut Superieur d'Electronique de Paris (ISEP), France, LETI, Commissariat À l'Energie Atomique et Aux Energies Alternatives (CEA-LETI), France
Abstract
A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh. This is achieved using negative differential resistance property of TFETs and storage capacitor leakage. uDRAM allows scaling of storage capacitor by 87% and 80% in comparison to DDR and eDRAMs, respectively. Bitcell area of 0.0275?m2 is achieved in 28nm FDSOI-CMOS and is scalable further with technology shrink. Estimated throughput gain is 3.8% to 18% in comparison to CMOS DRAMs by refresh removal. © 2017 IEEE.
Author-Keywords
DRAM, EDRAM, Metal-insulator-metal (MIM) capacitors, Tunnel FET
Index-Keywords
CMOS integrated circuits, Digital storage, Field effect transistors, Metal insulator boundaries, MIM devices, Bitcell, EDRAM, Embedded application, Estimated throughput, Metal insulator metal capacitor (MIM), Negative differential resistances, Storage capacitor, Tunnel FET, Dynamic random access storage
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