"Fully-Depleted-Silicon-On-Insulator (FDSOI) CMOS architectures are now in production at the 28nm and 22nm technology nodes by STMicrolectronics and Global Foundries [http://www.soiconsortium.org/fully-depleted-soi/presentations/SOI-Consortium-FD-SOI-Symposium-Sanjose-2016]. The great advantage of this technology, compared to the finFETs alternative, is the back-bias efficiency, i.e. the capability to play with an extra gate electrode (underneath the device), in order to tune the electrical characteristics. This enables saving dynamic power and thus for this technology to be highly competitive, especially for low-cost low-power Internet-of-Things (IoT) applications, which should be the growing market of the next decade.In order to leverage even more the back-bias capability for the next nodes, solutions exist for planar integration [L. Grenouillet et al, IEDM'12]. But even more opportunities can be provided by a 3-dimensional (3D) integration.LETI is a pioneer in the monolithic 3D CMOS integration [P. Batude et al., VLSI'15]. We have been developing technology and design kits (including spice model, parasitics extraction tools and design library) in order to assess, enable and benchmark this architecture not only for More-Moore but also for More-than-Moore roadmaps. The purpose of this MSc internship is to study the interest of the LETI 3D monolithic technology, namely CoolCubeTM, in improving the back bias capability of the planar FDSOI technology. Especially, the student will analyze, whether CoolCubeTM can extend a CMOS 14nm LETI planar FDSOI digital library with some specific Ultra-Low-Power 3D cells, with no or limited area penalty.This study is in-between CMOS technology and design. "