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Scaling of everything

Scaling of everything

Les besoins de demain reposent sur la nécessité de développer de nouveaux matériaux aux propriétés innovantes, essentiels pour innover dans tous les domaines et pour la compétitivité industrielle.


Published on 26 February 2017

Scaling of everything

Downscaling technologies are in great demand in relation to developing ultra-low power solutions for future IoT and disruptive computing, while miniaturization is required for smaller, lighter system packaging.

Computers have transformed society in the last 50 years; this is linked to the scaling of transistors and memory devices based on Moore’s law.
This scaling law is now reaching its limits although system-on-chip integration is tending towards heterogeneity.

In heterogeneous systems, CMOS, memories and sensors are co-integrated on chips to give ultra-low power solutions for the future IoT and disruptive computing. i is currently developing an image recognition system that mimics the neuronal network[1, 2] Fig 1.

Our in-depth knowledge of FDSOI CMOS devices and silicon nanowire has led to another research area: quantum calculation by developing quantum bits on silicon[3,4] Fig 2.

Future very small integrated systems will compute at very low energy using new paradigms and heterogeneous integration.

An increasing number of technologies are required in relation to miniaturization, advanced packaging and low weight for medical and transport applications, for example [5,6], Fig 3.



Fig.1



CMOS qubit device. a simplified 3-dimensional schematic of a SOI nanowire field-
effect transistor with two gates Gate 1 and Gate 2. Using a bias-T, Gate 1 is connected to a
low-pass-filtered line, used to apply a static gate voltage Vg1, and to a 20-GHz bandwidth line,
used to apply the high-frequency modulation necessary for qubit initialization, manipulation and
readout. b, Colorized device top view obtained by scanning electron microscopy just after the
fabrication of gates and spacers. c, Colorized transmission-electron-microscopy image of the device along a longitudinal cross-sectional plane.






Fig.3 Implantable Low Profile Silicon box





 Related publications in the scientific report :

[1] Experimental Demonstration of Short and Long Term Synaptic Plasticity Using OxRAM Multi k-bit arrays for Reliable Detection in Highly Noisy Input Data T. Werner, E. o, O. Bichler, A. i, E. Nowak, J.-F. Nodin, B. Yvert, B. o, L.Perniola proceedings of IEDM 2016

[2] D. Garbin, E. Vianello et al. "HfO2-Based OxRAM Devices as Synapses for Convolutional Neural  Networks" Electron s, IEEE Transactions on 62 (8), 2494-2501 (2015)

[3] Si CMOS Platform for Quantum Information Processing L. Hutin,, R. Maurand,  D. Kotekar-Patil et al. Proceeding sof VLSI 2016

[4] A CMOS silicon spin qubit, R. Maurand, X. Jehl, D. Kotekar Patil et al.

[5] System-on-Wafer: 2-D and 3-D Technologies for Heterogeneous Systems, JC Souriau; N Sillon; J n; et al. IEEE Transactions on Components, Packaging and Manufacturing Technology  2011, Volume: 1, Issue: 6 p: 813 - 824,

[6] Implantable device including a MEMS r and an ASIC chip encapsulated in a hermetic silicon box for measurement of cardiac physiological parameter JC. Souriau; L. Castagné; G. t; G. Simon et al. 2014 IEEE 64th Electronic Components and Technolog
y Conference (ECTC)

ble device including a MEMter and an ASIC chip encapsulated in a hermetic silicon box for measurement of cardiac physl parameter