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Second RISC-V Week

From 3/30/2021 to 4/1/2021
digital + présentiel: Hôtel Novotel Grenoble Centre, 7 place Robert-Schuman, Grenoble

IRT Nanoelec (EN)CEA TechInria, and OpenHW Group are organizing the “2nd RISCV week” as a phygital event (online and at sites : Rennes, Grenoble & Paris-Saclay)

RISC-V is a free and open ISA enabling a new era of processor innovation through open source collaboration. Hardware and software designers, be they industrials, academics, or individuals contributors, collaborate in the development of RISC-V cores, related IP, tools and software. This community delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation thanks to open source of both hardware and software.

This is the approach taken by the OpenHW Group, a member-driver organization that is industrializing the CORE-V family of RISC-V compliant processor cores. OpenHW Group is developing a full spectrum of verification plans, compilers, IDEs, simulators, and MCU designs. OpenHW Group has recently released a fully verified 32-bit 4 stage core (CV32E40P) and is in active development of 64/32 bit application class core, together with follow-on cores in the CV32 family.

Practical information

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