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Integrated circuit design

High-performance computing gets new technology brick

​​​Leti, a CEA Tech institute, has developed a new on-chip communications system to improve high-performance computing. The technology is faster and more energy-efficient than current solutions and is compatible with 3D architectures.​

Published on 28 June 2016

​The number of applications that require high-performance computing (HPC) is on the rise. Leti has added to its HPC technology lineup with a new hardware-plus-software communications solution.

This new technology brick, which is compatible with 3D integrated circuit architectures, makes it possible to transfer data between processors via a network-on-chip (NoC), for more powerful, energy-efficient computing. Our researchers boosted computing power and slashed energy consumption by stacking chips on top of each other in a single enclosure or by placing the chips side by side on a silicon interposer. The chips exchange data via the new communications network.

A demonstrator system developed under the IRT Nanoelec 3D integration program​​ was presented at ISSCC 2016 in San Francisco. The demo was a success, with very good chip-to-chip data transmission speeds—in the hundreds of Mbits/s—for a chip measuring just 40 µm x 40 µm. Even better, the chip needs 20 times less energy for data transmission than chips placed on an electronic circuit board. This new IP is compatible with standard remote direct memory access-type software used for data transmission and could be of interest to industrial partners for virtual-server migration applications.

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