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Published on 7 December 2023
Research FieldElectronics and microelectronics - Optoelectronics


ThemeEngineering sciences


Electronics and microelectronics - Optoelectronics Engineering sciences DRT DCOS S3C LDQC Grenoble
Low temperature process modules for 3d coolcube integration : through the end of roadmap
3D sequential integration is envisaged as a possible solution until the end of CMOS roadmap. Different process modules have been developped @ 500°C for planar FDSOI technology in a gate first process. However, regarding bottom transistor level stability in CoolcubeTM integration, and yield consideration, the need to reduce further the top transistor temperature down to 450°C should be explored. The post-doc will have in charge the development of specific technological modules at low temperature both 500°C and 450°C for FDSOI planar devices to acquire a solid knowledge in low temperature CMOS process integration. The specific low temperature gate module will be addressed on planar devices. The threshold voltage modulation will also be studied. The work will be performed in collaboration with the technological platform process of LETI for the low temperature modules development. The electrical characterization in collaboration with the characterization laboratory and the TCAD simulations team of LETI.
Département Composants Silicium (LETI) Service des Composants pour le Calcul et la Connectivité Laboratoire Dispositifs Quantiques et Connectivité
FENOULLET-BERANGER Claire CEA DRT/DPFT CEA-Grenoble 17 rue des Martyrs 38054 GRENOBLE CEDEX 04 38 78 56 77
Start date1/3/2019

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