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PsD-DRT-20-0043

Published on 7 December 2023
PsD-DRT-20-0043
Research FieldElectronics and microelectronics - Optoelectronics

Domaine-SSolid state physics, surfaces and interfaces

ThemeEngineering sciences

Theme-SCondensed matter physics, chemistry & nanosciences

Domaine
Electronics and microelectronics - Optoelectronics Engineering sciences Solid state physics, surfaces and interfaces Condensed matter physics, chemistry & nanosciences DRT DCOS SCCS LSM Grenoble
Title
Modeling of trapping and vertical leakage effects in GaN epitaxial substrates on Si
Abstract
State of the art: Understanding and modeling vertical leakage currents and trapping effects in GaN substrates on Si are among the crucial subjects of studies aimed at improving the properties of GaN power components : current collapse and Vth instabilities reductions, reduction of the leakage current in the OFF state. Many universities [Longobardi et al. ISPSD 2017 / Uren et al. IEEE TED 2018 / Lu et al. IEEE TED 2018] and industrials [Moens et al. ISPSD 2017] are trying to model vertical leakages but until now, no clear mechanism has emerged from this work to model them correctly over the entire range of voltage and temperatures targeted. In addition, modeling the effects of traps in the epitaxy is necessary for the establishment of a a robust and predictive TCAD model of device. For LETI, the strategic interest of such a work is twofold: 1) Understanding and reducing the effects of traps in the epitaxy impacting the functioning of GaN devices on Si (current collapse, Vth instabilities…) 2) Reaching the leakage specifications @ 650V necessary for industrial applications. The candidate will have to take charge in parallel of the electrical characterizations and the development of TCAD models: A) Advanced electrical characterizations (I (V), I (t), substrate ramping, C (V)) as a function of temperature and illumination on epitaxial substrates or directly on finite components (HEMT, Diodes, TLM ) B) Establishment of a robust TCAD model integrating the different layers of the epitaxy in order to understand the effects of device instabilities (dynamic Vth, dynamic Ron, BTI) C) Modeling of vertical conduction in epitaxy with the aim of reducing leakage currents at 650V Finally, the candidate must be proactive in improving the different parts of the substrate
Location
Département Composants Silicium (LETI) Service Caractérisation, Conception et Simulation Laboratoire de Simulation et Modélisation
Pcontact
JAUD Marie-Anne CEA DRT/DCOS//LSM CEA-LETI, Minatec 17 rue des Martyrs 38054 Grenoble cedex 09 04-38-78-24-26
Start date 
Contact personmarie-anne.jaud@cea.fr

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