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High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology

Published on 29 March 2018
High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology
Description
 
Date 
Authors
Brocard M., Boumchedda R., Noel J.P., Akyel K.C., Giraud B., Beigne E., Turgis D., Thuries S., Berhault G., Billoint O.
Year2017-0091
Source-Title2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
Affiliations
Univ. Grenoble Alpes, Grenoble, France, STMicroelectronics, 850 rue Jean Monnet, Crolles, France, CEA, LETI, MINATEC Campus, Grenoble, France
Abstract
In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar 6T SRAM bitcell in 14nm FD-SOI technology. © 2016 IEEE.
Author-Keywords
3D design, 3D sequential, Monte Carlo simulation, SRAM 4T Bitcell
Index-Keywords
Finite difference method, Intelligent systems, Microelectronics, Silicon on insulator technology, 3-d designs, 3D sequential, Bitcell, Critical operations, High density SRAM, Post layout simulation, SOI transistors, Technology-based, Monte Carlo methods
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