Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies
| Description | |
| Date | |
| Authors | De Conti L., Bedecarrats T., Vinet M., Cristoloveanu S., Galy P. |
| Year | 2017-0356 |
| Source-Title | 2017 IEEE International Conference on IC Design and Technology, ICICDT 2017 |
| Affiliations | STMicroelectronics, 850 rue Jean Monnet, Crolles, France, IMEP, 3 Parvis Louis Néel, CS 50257, Grenoble Cedex 1, France, CEA LETI, 17 avenue des martyrs, Grenoble Cedex 9, France |
| Abstract | This paper presents a new device named the Gated Diode merged BIMOS (GDBIMOS) which is fabricated using the 28nm UTBB FD-SOI high-k metal gate CMOS technology. It is highly reconfigurable and topologically robust for ESD protection. The suitable ESD window is achieved thanks to doping adjustment and to different possible gate connections. © 2017 IEEE. |
| Author-Keywords | BIMOS, Electrostatic Discharges, FD-SOI, Gated Diode, MOSFET, SCR |
| Index-Keywords | CMOS integrated circuits, Diodes, Electrostatic devices, Electrostatic discharge, Finite difference method, Thyristors, BIMOS, CMOS technology, ESD protection, FD-SOI, Gated diodes, HIGH-K metal gates, MOS-FET, Reconfigurable, MOSFET devices |
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| Link | Link |