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3DIP: An iterative partitioning tool for monolithic 3D IC

Published on 29 March 2018
3DIP: An iterative partitioning tool for monolithic 3D IC
Description
 
Date 
Authors
Berhault G., Brocard M., Thuries S., Galea F., Zaourar L.
Year2017-0342
Source-Title2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
Affiliations
CEA, Leti, Minatec Campus, Grenoble, France, CEA, LIST, Nano-INNOV, 8 avenue de la Vauve, Palaiseau, France
Abstract
CoolCubeTM is a monolithic 3D (M3D) technology offering a vertical density of integration 20 times higher than face to face copper hybrid bonding (F2F Cu-Cu), thanks to ultra-thin Monolithic Inter-tier Vias (MIVs). In this work, we propose a new partitioning tool exploiting this characteristic for 2-tier Cell-on-Cell ICs before placement. It is based on a fast and iterative algorithm that explores the space of solutions and minimizes the estimated cost of wires with balanced area between tiers without limiting the number of MIVs. A mathematical formulation of the 3D partitioning problem and a comprehensive framework, based on simulated annealing (SA) algorithm coupled with a dedicated cost function, are detailed and compared with Min-Cut (MC) partitions commonly used. It appears that our solution can decrease the estimated total cost of wires by 41% and 45% for the LDPC and FFT/AES units. It also reduces the total cost of wires by 30% to 44% compared to the MC algorithm for the same units and with no significant increase in runtime. © 2016 IEEE.
Author-Keywords
3D partitioning, CoolCube™, High Density IC, Monolithic 3D
Index-Keywords
Cost estimating, Cost functions, Costs, Estimation, Functions, Integration, Iterative methods, Monolithic integrated circuits, Simulated annealing, Timing circuits, Wire, 3D partitioning, Estimated costs, Hybrid bonding, Iterative algorithm, Iterative Partitioning, Mathematical formulation, Partitioning problem, Simulated annealing algorithms, Three dimensional integrated circuits
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