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Towards on-line estimation of BTI/HCI-induced frequency degradation

Published on 29 March 2018
Towards on-line estimation of BTI/HCI-induced frequency degradation
Description
 
Date 
Authors
Altieri M., Lesecq S., Beigne E., Heron O.
Year2017-0257
Source-TitleIEEE International Reliability Physics Symposium Proceedings
Affiliations
Univ Grenoble Alpes, CEA, Leti, Grenoble, France, CEA, List, Université Paris-Saclay, Gif sur Yvette, France
Abstract
This work proposes a new bottom-up approach for on-line estimation of circuit performance loss due to BTI/HCI effects. Built on the top of device-level models, it takes into account all factors that impact global circuit aging, namely, process, topology, workload, voltage and temperature variations. The proposed model is fed by voltage and temperature monitors that on-line track dynamic variations. This allows an accurate assessment of the evolution of the circuit critical path delays during its operation. Its accuracy is evaluated here on two circuits implemented in 28nm FD-SOI technology. © 2017 IEEE.
Author-Keywords
BTI, Circuit-level model, HCI
Index-Keywords
Dispensers, Frequency estimation, Human computer interaction, Integrated circuit testing, Bottom up approach, Circuit performance, Circuit-level models, Critical path delays, Global circuit, On-line estimation, Temperature monitor, Temperature variation, Delay circuits
ISSN15417026
LinkLink

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