CEA, LETI, MINATEC Campus, Grenoble, France, STMicroelectronics, 850 Rue Jean Monnet, Crolles, France, Now with IMEC, Kapeldreef 75, Leuven, Belgium

In this paper, dynamic variability (DV) induced by BTI is deeply investigated in nano-scaled devices by means of statistical measurements and modeling. The impact of a single charge q on Vt is first investigated through 3D electrostatic simulations. In planar devices, this MC modeling allows proving that the average Vt shift induced by a single q denoted ?t is inversely proportional to the device area. In trigate 3D transistors, BTI trapping not only occurs at the top surface (TS) oxide but also at the device sidewalls (SW). For ?fet Nanowire, this implies that ?t exhibits a complex variation with device scaling unlike in planar structures. In contrast, Finfet rather behaves as a vertical planar device for which SW plays now the role of TS. Finally the impact of device scaling on NBTI degradation is thoroughly studied in 3D technologies. Enhanced NBTI is measured on narrower devices. This phenomenon is well explained and reproduced by 3D MC simulations considering a poorer quality of the SW gate oxide with respect to its TS counterpart. © 2017 Elsevier Ltd

BTI, Defect Centric Model, Dynamic variability, Finfet, Monte Carlo simulation, Nanowire

FinFET, Intelligent systems, MOS devices, Nanowires, Device-scaling, Dynamic variability, Electrostatic simulations, Measurements and modeling, Modeling of dynamics, Nano-scaled devices, Planar devices, Planar structure, Monte Carlo methods