Advanced packaging technology for heterogeneous system-in-package (SiP)
What is fan-out wafer-level packaging technology?
CEA-Leti offers a competitive fan-out wafer-level packaging technology using 8” wafers. Based on the reconstruction of substrates around individual chips, this technology has become an iconic part of any “More than Moore” strategy, fueling high-potential multi-chip system-in- package (SiP) since the mid-2000s.
Eliminating the need for intermediate laminated substrates has enabled the integration of high performance systems at a reduced cost and footprint. It has also paved the way for applications that would have been difficult to address with conventional packaging.
Applications:
RF front-end modules for wireless communications and radar
- Hybrid modules combining III-V, SiC and CMOS
- Integration of passive components
- Antenna in package
High-speed optical interconnect
- VCSEL, PIN Diode and silicon photonics system-in-package
Sensing systems
- Integration of various sensors such as MEMS with drivers IC
Expertise:
From design fabrication down to UBM level, CEA-Leti offers extensive expertise in fan-out wafer-level packaging to industrial partners on the lookout for competitive heterogeneous system-in-package (SiP) solutions.