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Advanced packaging technology for heterogeneous system-in-package (SiP)
What is fan-out wafer-level packaging technology?
CEA-Leti offers a competitive fan-out wafer-level packaging technology using 8” wafers. Based on the reconstruction of substrates around individual chips, this technology has become an iconic part of any “More than Moore” strategy, fueling high-potential multi-chip system-in- package (SiP) since the mid-2000s.
Eliminating the need for intermediate laminated substrates has enabled the integration of high performance systems at a reduced cost and footprint. It has also paved the way for applications that would have been difficult to address with conventional packaging.
High-speed optical interconnect
End result − diced SiP
Fully populated wafer heterogeneous loading of Si and SiC dice
Pealing of thermal tape used for temporary bonding
Example of thermal management:
heat spreader with thermal contact
on high power amplifier backside
CEA is a French government-funded technological research organisation in four main areas: low-carbon energies, defense and security, information technologies and health technologies. A prominent player in the European Research Area, it is involved in setting up collaborative projects with many partners around the world.