Silicon PIC Platform
Photonics technologies convergence on silicon CMOS platform
CEA-Leti’s fabrication platform for silicon photonic integrated circuits (PIC) enables large-scale integration of active and passive devices in a flexible CMOS-compatible process.
Beyond silicon, the platform also offers integration of SiN and III-V bonded epi layers on the same wafer, providing the advantages of each material. The convergence of various photonic platforms combined with CEA-Leti’s multi-material process helps address numerous applications with the same technology.
Applications
Several applications come with this photonicstechnologies convergence on a Si CMOS platform, including: -
Communication: telecom, datacom, 5G infrastructures, quantum cryptography for cybersecurity
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Computing: computer communication for high performance computing (HPC), quantum computing and neuromorphic computing for AI
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Sensing: optical gas sensing, structural health monitoring and 3D sensing such as LIDAR
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What's new?
Benefits of this convergence offer CEA-Leti’s partners a greater number of functions on photonic integrated circuits (PIC), fabricated on an advanced CMOS-compatible platform. CEA-Leti’s key achievements: - Mature device library for O-band and C-band in a process design kit (PDK), compatible with conventional CAD tools
- Small fetaure size and low sidewall roughness
- III-V integration on CMOS-compatible process through collective die bonding
- Multilayer Si/Si or SiN/Si for 3D photonics
- 2D beam steering based on SiN OPA
- Tunable DBR, DFB, racetrack lasers
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SOI photonics cross section
ULL-SiN cross section
CEA-Leti's also offers a state-of-the-art platform for ultra-low loss silicon nitride (ULL-SiN) on 200 mm wafers, based on 800 nm Si3N4 LPCVD film on 3 μm insulation oxide.
What’s next?
CEA-Leti’s Optics and Photonics Division is working on:
- Focus on ultra low insertion loss and high efficiency Si & SiN devices
- Develop high efficiency NbN Superconducting single photon detector (SSPD)
- Introduce new materials
- Keep on the improvement of wafer scale heterogeneous integration