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Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems (APECS)

​​​​​​Three dimensions, unprecedented potential


Published on 27 April 2026


Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems (APECS)​


Three dimensions, unprecedented potential 


 

Starting date: Dec 16, 2024 >June ​16 2028 ​​
Lifetime
: 4.5 years

 

Program in support: EU Chips Act

​ ​ 

Status of project: on going


CEA-Leti's contact:                         
Mathilde Billaud​​
                                      
 

Project Coordinator: CEA-Leti 
Department: DCOS/ DSYS​

Partners:   

  • ​​ ​Fraunhoher Gesellschaft
  • Research Fab Microelectronics Germany (FMD)​
  • Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik​
  • IHP GmbH - Leibniz Institute for High Performance Microelectronics​
  • TU Graz​​
  • VTT
  • Imec
  • CEA-LETI​​
  • FORTH​
  • Institute of Microelectronics of Barcelona (IMB-CNM-CSIC)
  • INL

Target marketTelecommunications, AI/machine learning, medical & scientific instrumentation, High-perfo​rmance computing, sensor systems, industrial manufacturing​



Investment: € 730 million over 4,5 years

​​


Website

Vision

Inn​​ovating right where European industry needs it most​

​To be the leading European platform for advanced packaging and heterogeneous integration innovation, APECS envisions a future where the European semiconductor industry is not only internationally competitive, but also a driving force behind the next generation of integrated systems.

By bringing together diverse technologies, fostering multi-level collaboration, and pro-viding seamless access to cutting-edge solutions, APECS aims to build a resilient and thriving community of interest tha​t enables European companies, from Startups through SMEs to industry leaders, to play a key role in the global semiconductor market.

Pu​​rpose

Connecting and collaborating

The APECS Pilot Line is dedicated to catalyze innovation and cooperation across Europe's semiconductor landscape. Our purpose is to bridge the gap between research, industry, and policy to drive the continent's competitiveness in advanced packaging and heterogeneous integration.


Pioneering Innovation

APECS leads the way in heterogeneous integration including various advanced packaging types by providing diverse technologies into a single platform that enables the innovative production tailored to Europe's industry needs. In the proposed pilot line, new functionalities will be activated as part of the System Technology Co-Optimization (STCO) ecosystem and integration technologies will be standardized. The platform of capabilities to be developed will include novel characterization, quality assurance, testing & reliability (CTR) methodologies.


Facilitating multilevel Cooperation

APECS fosters cooperation between European RTOs, industry, academia, and policy makers to drive innovation through technology transfer, small volume prototyping and collaborative research, bringing a community of interest around next generation technologies for advanced packaging and heterogeneous integrated systems.


Driving European competitiveness at peak performance

APECS supports the creation of a robust, secure, and resilient European semiconductor supply chain, easing access for SMEs and startups to advanced technologies, helping them prototype and scale up production.


Bonding around heterogeneous integration and advanced packing

The platform of capabilities to be developed will include novel characterization, quality assurance, testing & reliability (CTR) methodologies and a System-Technology Co-Design (STCO) framework to ensure quality, reliability and fast production ramp-up in collaborating manufacturing organizations.


Catalyzing fresh prospects f​​or regional ​​chip manufacturing

APECS strengthens European SMEs and start-ups by providing access to critical services, skills and training, opening up a brand new landscape of new markets and opportunities for European business models and a low-threshold, easily scalable industrial transfer of these newly developed innovations.​​​




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​​Within the framework of the APECS pilot line will be possibl​e to fu​rther expand the R&D infrastructure for semiconductor technologies and a​​p​plications in the coming year​s.​

​​Post-CM​OS pressure sensor chiplets ​​with wafer l​evel ​packaging ​before dicing.



Credit: loewn | ​​Be​​rnh​ard ​​Wolf​
 

Credit: Fra​unh​​ofer​ ISIT​​​