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2020 Symposia on VLSI Technology and Circuits

From 6/14/2020 to 6/19/2020
Web conference

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The edition 2020 will be outstanding with 12 papers accepted 
With a record acceptance rate of over 70%, CEA-Leti and its partners will present a dozen of scientific papers during the 2020 Symposia on VLSI Technology and Circuits. Given the global health concerns, guests are invited to attend virtual sessions. Learn more on the conference website:

CEA-Leti papers



​First author 

​ First CEA-Leti author

  Affiliation of the other   authors     


7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

​Sylvain Barraud (CEA-Leti)

​Sylvain Barraud


All-operation-regime characterization and modeling of drain current variability in junctionless and inversion-mode FDSOI transistors

​​David Bosch (CEA-Leti)

​David Bosch


28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D Sequential Integration: yield and reliability analysis

​C.Cavalcante (CEA-Leti)



First demonstration of low temperature (≤500°C) CMOS devices featuring functional RO and SRAM bitcells toward 3D VLSI integration

​Claire Fenouillet-Beranger (CEA-Leti)

​Claire Fenouillet-Beranger


Enabling UTBB Strained SOI Platform for Co-integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-like Device Architecture
​Chen SUN
(National University of Singapore)
​Vincent Barral


Nanosecond Laser Anneal (NLA) for Si-implanted HfO2 Ferroelectric Memories Integrated in Back-End Of Line (BEOL)

Laurent Grenouillet (CEA-Leti)

​Laurent Grenouillet 

​NamLab (GE)


Vertical Heterojunction Ge0.92Sn0.08/Ge GAA Nanowire pMOSFETs: Low SS of 67 mV/dec, Small DIBL of 24 mV/V and Highest Gm,ext of 870 μS/μm
Mingshan LIU (PGI 9, Jülich)
​Jean-Michel Hartmann
​Aachen University (GE)


ExaNoDe: combined integration of chiplets on active interposer with bare dice in a multi-chip-module for heterogeneous and scalable high performance compute nodes
​Pierre-Yves Martinez (LIST)
​Jean Chabonnier
​3IT Univ. Sherbrooke (CA)
LN2, CNRS, Sherbrooke (CA)


A SiOx RRAM-based hardware with spike frequency adaptation for power-saving continual learning in convolutional neural networks
I. Munoz-Martin (Politecnico di Milano)
​Jean-François Nodin


Variability Evaluation of 28nm FD-SOI Technology at Cryogenic Temperatures down to 100mK for Quantum Computing
​Bruna Cardoso Paz (CEA-Leti)

​Bruna Cardoso Paz



SamurAI: a 1.7MOPS-36GOPS Adaptive Versatile IoT Node with 15,000x Peak-to-Idle Power Reduction, 207ns Wake-up Time and 1.3TOPS/W ML Efficiency

​Ivan ​Miro-Panades (LIST)

​Clément Jany



A 3.0μW@5fps QQVGA self-controlled wake-up imager with on-chip motion detection, auto-exposure and object recognition​Arnaud Verdant (CEA-Leti)
Arnaud Verdant


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