EVENT
Discover CEA-Leti’s latest results in Microelectronics & Packaging
The conference program will focus on industrial needs and trends and on academic long-term solutions. The event brings together researchers, innovators, technologists, business and marketing managers with an interest in semiconductor packaging.
MEET CEA-LETI’S EXPERTS
This year, CEA-Leti's booth will exhibit demonstrations of photonic interposers, 3D heterogeneous integration, hybrid bonding, and Chip-In-Flex technology. Come and discuss lastest achievements in terms of microelectronics and packaging.
CEA-Leti’s tech demos — Booth 4
Starac
Chiplet-based Optical Network on Chip (ONoC)
Chip-in-Flex
Low-cost, miniaturized ultrasound emitters/ receivers
3D integration for HPC & AI
Active interposer technologies for advanced chiplet-based systems: CMOS to photonic and quantum architectures
Next generation hybrid bonding
An enabling technology for new architectures
DISCOVER CEA-LETI’S MAJOR SCIENTIFIC RESULTS AT EMPC
With 8 papers, the institute will present this year's major scientific results at EMPC, including the following topics:
- Quantum Packaging
- Optical Network on Chip / CPO
- Fan-Out Wafer-Level Packaging
- 3D Heterogeneous Integration
CEA-Leti scientific papers
16/Sept/2025, 11:15am - 12:30pm
S 1D: Assembly and Manufacturing
Location: Makalu
David Henry
Development of advanced screen-printing technology for flip-chip transfer of electronic components
16/Sept/2025, 1:50pm-3:05pm
S 2B: Interconnection Technologies
Location: Kilimandjaro
Arnaud Garnier
Characterization of Chip-to-Wafer Interconnects with Thick Gold Finish for Fan-Out Wafer-Level Packaging RDL First Integration
17/Sept/2025, 11:00am-12-15pm S 4D: POSTER SESSION #1 Location: Makalu
Céline Feautrier
Thermomechanical study for stress-management of silicon photonics interposers
16/Sept/2025, 11:15am-12:30pmS 1B: Interconnection Technologies
Location: Kilimandjaro
Meriem Guergour
Stability of the Superconducting β-Sn Phase at Low Temperatures for 3D Cryogenic Packaging
17/Sept/2025, 1:35pm-3:15pm
S 5B: Optoelectronics
Location: Kilimandjaro
Jean Charbonnier
TSVs mechanical stress measurements on silicon wave-guide using phase shift Interferometry
17/Sept/2025, 3:50pm-5:05pm
S 6A: System in Package
Location: Auditorium
Perceval Coudrain
Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration
16/Sept/2025, 1:50pm-3:05pm
S 2B: Interconnection Technologies
Location: Auditorium
Mel Dahys
Fabrication of Indium Interconnections for Flip-chip Assembly on Single Die
17/Sept/2025, 1:35pm-3:15pm
S 5B: Optoelectronics
Location: Kilimandjaro
Jean Charbonnier
Impact of TSV Mechanical Stress on Silicon Wave-guides Using Phase Shift Interferometry
17/Sept/2025, 3:50pm-5:05pm
S 6A: System in Package
Location: Auditorium
Thierry Mourier
Advancing Fan-Out Wafer-Level Packaging for III-V/CMOS Optoelectronic Transceiver SiP Integration
DON'T MISS SÉBASTIEN DAUVÉ'S TALK ON CO-OPTIMIZATION FOR ADVANCED 3D & HETEROGENEOUS INTEGRATION
Session: Keynote 5
September 17, 9:30 a.m - 10:15 p.m
System Technology Co-optimization for Advanced 3D & Heterogeneous Integration
Sébastien Dauvé, CEO, CEA-Leti
ABOUT EMPC 2025
The European Microelectronics and Packaging Conference (EMPC 2025) is the premier international conference for microelectronics packaging, owned and sponsored by IMAPS-Europe and co-sponsored by IEEE-EPS.
More information on EMPC's website.