CEA-Leti, STMicroelectronics, SOITEC and Grenoble INP-UGA and are very proud to announce they will organize the 51th IEEE European Solid-State Device Research Conference ESSDERC and the 47th IEEE European Solid-State Circuits Conference ESSCIRC from September 6 fully virtual
ESSCIRC-ESSDERC is the most important and prestigious scientific conference on integrated circuits design and technology of in Europe. 600+ participants are expected (industry and academia) + students (electrical engineering, microelectronics, etc.) from all around the world. ESSCIRC and ESSDERC constitute the annual European forum for research in microelectronics. The increasing level of integration of the system-on-a-chip design requires ever-deeper interaction among technologists, device experts, IC designers and system designers.
Program of session papers, virtual educational events (workshops and tutorials) and plenary talks is now available!
The program of the full virtual conference will be organized in 3 sequences:
PREAMBLE WEEK: the virtual platform will open on September 6, 2021. All presentations will be available on demand until November 30, 2021.
INTERACTIVE CONFERENCE WEEK: September 13 - 17, 2021 - Live broadcast of Joint plenary and Key note presentations & Live Q&A sessions for all other conference sessions
Monday September 13, 2021 (15:45 - 16:30
Jean-René Lèquepeys
+ Marc Duranton, Susana Bonnetier, Sandrine Catrou, Richard Fournel, thomas Ernst, Laurent Hérault...
| Overcoming the Data Deluge Challenges with Greener Electronics - Monday September 13, 2021 :15:45 - 16:30
The purpose of this paper is to propose scientific and technical directions to reach global data and power sobriety while preserving computational efficiency. We present nine opportunities to lower the power consumption of computing units. A growth factor of 100 to 1000 in energy efficiency is achievable in the next 10 years if we take full advantage of all the potential improvements, working simultaneously at all five levels of the technological ecosystem (process steps, circuits, architecture, software and algorithms)
Learn more
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EDUCATIONAL WEEK: September 20-22, 2021, Live Q&A sessions for all Educational Events
Here is the CEA-Leti and CEA-List prime author papers list:
Title
| Speakers
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Parasitic Capacitance Analysis in Short Channel MIS-HEMTs GaN
| R. Kom Kammeugne et al
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Analysis of MIS-HEMT Device Edge Behavior for GaN Technology Using New Differential Method,
| R. Kom Kammeugne et al
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Wafer-Scale Fabrication of Biologically Sensitive Si Nanowire FET: from Ph Sensing to Electrical Detection of DNA Hybridization
| R. Midahuen et al.
|
Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: the Effect of Back Bias on Drain Current and Transconductance,
| M. Cassé et al.
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Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications,
| B. Cardoso Paz et al.
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Influence of Substrate Resistivity on Porous Silicon Small Signal RF Properties,
| E. Angendre et al.
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Reliable Method for Low Field Temperature Dependent Mobility Extraction at Al2O3/GaN Interface
| B. Rrustemi et al.
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Overcoming the Data Deluge Challenges with Greener Electronics,
| J-R. Lequepeys et al.
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Toward 6G: from New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms,
| E. Calvanese Strinati et al.
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A 108 Gb/S 64-QAM CMOS D-Band Rx with Integrated Lo Generation
| A. Hamani et al.
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A 84.48Gb/S 64-QAM CMOS D-Band channel-Bonding Tx front-End with Integrated multi-Lo Frequency Generation
| A. Hamani et al.
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Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive Ram Bridges
| M. Ezzdeen et al.
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Ultrahigh-Density 3-D Vertical RRAM with Stacked Junctionless Nanowires for In-Memory-Computing Applications
| M. Ezzdeen et al.
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