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ESSERC 2026

From 9/7/2026 to 9/10/2026
Palma de Mallorca, Spain

​​​​​​​​​​​​​​​​​​​​EVENT

Discover CEA-Leti's scientific excellence at ESSERC 

CEA-Leti will be represented at ESSERC with five scientific papers and presentations in the workshops and tutorials.​


MAJOR SCIENTIFIC RESULTS

With 5 papers, the institute will present this year’s major scientific results at ESSERC, including the following topics:  

  • Memories
  • Edge AI
  • Nanosheet​
  • 3D
  • Power circuit

Devices for neuromorphic applications - C1L-A​​

Tuesday September 08, 2026
11:00 am - 1:00
​ pm
Sala MAGNA​

Fabien Roze
Sylvain Barraud
Jean-Michel Pedini
Vincent Larrey
Frank Fournel
Jean-Michel Hartmann
​Karine Abadie

Fabrication of Hybrid Channel CFET Stack by Innovative Wafer-to-Wafer Bonding and Nanosheet Patterning​

Devices for optoelectronics sensing - A2L-H ​​

Tuesday September 08, 2026
2:00 pm - 4:10​ pm
Sala GRANADOS I

Ahmed Machmach
Christoforos Theodorou
Sébastien Place
Thomas Nassiet
Frederic Lalanne
Christian Gardin
​​

Nmos SOI Source Follower Floating Body Effects Mitigation and Pixel Level Induced Noise Modeling in 3D Sequentially Integrated BSI CIS ​​​​

LLMs, Transformers, and Generative AI Accelerators - C1L-E​​

Thursday September 10, 2026 10:40 am - 1:00 pm
Sala TURINA

Joaquin A. Cornejo
Filipe Pouget
Amelie Poullot
Raphael Gras
Dominique Bousquet
Nicolas Lebouleux
​Tarun Chawla​

BumbleBee: A 3 mW Fused-Kernel Flash Attention Edge AI Co-Processor in 18 nm FD-SOI CMOS

Advanced 3D technology for logic and memory devices​ - A1L-A​​

Thursday September 10, 2026 10:40 am - 1:00 pm
Sala MAGNA​

Yann Beilliard
Lanig Le Meur
Simone D’Agostino
Liam Hosier
Simon Martin
Carine Jahan
François Andrieu
Elisa Vianello ​

Statistical Study of HZO-Based Ferroelectric Capacitive Memories Integrated in 22 nm FDSOI BEOL

Hybrid and Switched-Capacitor Converters for Dense Power - C1L-C​​

Thursday September 10, 2026 10:40 am - 1:00 pm
Sala ALBENIZ

​Justin Pabot
Yasser Moursy
Maxime Lecomte
Romain Wacquez
​Gaël Pillonnet​

On-Chip SCC Topologies for Security Enabling 50% Power Reduction and 114× Attack Traces


TUTORIALS & WORKSHOPS​


  ​​​​​Monday, September 7, 2026​​​​

​  CEA-Leti ​Expert​

​​ ​​​​C​ont​ributio​​n​​​​​ ​

​Top​ic​​​​

​​​​​​Elisa Vianello

Tutorial​ speaker T1

In-Memory Computing for Trustworthy Edge AI: From Bayesian Methods to On-Chip Learning​​

​​​Gaël Pillonnet

Tutorial chair T5b

Power Management Techniques for Low-Power Edge and IoT Devices

​​Lina Kadura
CEA-Liten​

Workshop speaker W1

Printed Low Voltage OTFT Technology for Neuromorphic Circuits

Dominique Noguet

Workshop co-chair W2

Joint Workshop FAMES Pilot Line -SiNANO Institute: FDSOI Pilot Line Insights and Perspectives

Thierry Poiroux

Workshop speaker W2

Next Generations of FD-SOI Technology for Low-Power and RF Applications

Gabriel Parès

Workshop speaker W2

FAM​ES Achievements for Embedded Non-Volatile Memories in Europe

Alexandre Reinhardt

Workshop speaker W2

Solidly Mounted Lithium Niobate Bulk Acoustic Wave Filters for the FR3 Range

Daphnée Bosch​​

Workshop speaker W2

Advancing 3D Sequential Integration: Process Innovations and Future Applications

Emmanuel Ollier

Workshop speaker W2

The Rise of Heterogeneous Integration and 3D Archi​tectures as Key Enablers in the AI Era

Dominique Morche​​

Worksho​p speaker W8

Multi-Antenna T​ransceivers Exploiting Spatial Processing​​


​​

​Meet FAMES at ESSERC 2026 in Mallorca​

On 7 September 2026, FAMES and the SiNANO Institute will host a dedicated half-day workshop entitled: “FDSOI Pilot Line Insights and Perspective” This session will be the first opportunity to present in-depth technical results from the FAMES Pilot Line on the development of 10 nm and 7 nm FD-SOI technologies. ​​

 

Sept. 7, 2026​ | ​Palma de Mallorca, Spain​​​​​


FDSOI Pilot Line Insights and Perspective ​

A dedicated workshop by FAMES & SiNANO Institute​



ABOUT ESSERC

The aim of ESSERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary.

DL_Icon.pngMore information on ​​ESSERC’s website


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Practical information

From 09/07/2026 to 09/10/2026  | ​Palma de Mallorca, Spain

Web​site​​​

 ContactFrançois Andrieu  with any questions.​​


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CEA-Leti contact

François Andrieu

Head of memory lab, CEA-Leti







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