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ESTC - Electronics System-Integration Technology Conference

From 9/9/2026 to 9/11/2026
Helsinki, Finland

​​​​​​​​​​​​​​​​​EVENT

Discover CEA-Leti’s latest results in 3D & packaging​​

CEA-Leti experts will be onsite at CEA-Leti's booth and available to discuss the findings of three papers on heterogeneous integration​​



COME AND MEET CEA-LETI'S EXPERTS​

This year, CEA-Leti’s booth will exhibit 3D Chiplet integration. Come and discuss lastest achievements in terms of 3D and packaging.​​


CEA-Leti live demonstrator at ESTC 2026​

3D Chiplet Integration

Optimizing power, performance, area, cost, and environmental impact with heterogeneous 3D integration​​

CEA-Leti's 3D integration technologies respond to tomorrow’s challenges in a wide range of applications, including high-performance computing (HPC), AI, copackage optics, RF integration, quantum computing, power delivery, and also imagers and displays.​

 


DISCOVER CEA-LETI’S MAJOR SCIENTIFIC RESULTS AT [NOM DE LA CONFERENCE]

With 3 papers, the institute will present this year’s major scientific results at ESTC, including the following topics:  

  • TSV
  • Heterogeneous integration
  • Environmental assessment or FOWLP​


Scientific papers​​​

Wednesday, September 9
3:50 - 4:15 pm

AP 1: Substrate Innovation

​David Henry (1),
Aurélia Plihon (1),
Olivier Valorge (1),
Michael Bertucchi (1),
Yohann Rabault (1),
Catherine Brunet-Manquat (1),
Victor Milon (2),
Pascal Chevalier (2),
Baptiste Rault (1)
​​
(1) CEA LETI, France;
​(2) STMicroelectronics, France

Development of Middle Through Silicon Vias (TSV Mid) and Integration in Advanced SiGe BiCMOS Technology for Optical Interconnects

Thursday, September 10​
4:35 pm - 5:00 pm

AP 5: Advances in Materials and Processes

​Samuel Suhard (1),
Jaber Derakhshandeh (1),
Mélissa Najem (2),
David Henry (2),
Eduardo Coutino (1),
Vasiliki Kosma (1),
Frank Windrich (3),
Anne Jourdain (1),
Eric Beyne (1),

(1) Imec, Belgium;
(2) CEA-Leti France;
(3) ​Fraunhofer IZM, Germany

Heterogeneous Integration of Die to Wafer Microbumps Bonding and Hybrid Cu Bonding on a Single Interposer

Friday, September 11
11:00 am - 12:15 ​pm

AP 5: Advances in Materials and Processes

​Mathilde Billaud,
Aurore Sorrel,
Laetitia Castagne,
Arnaud Garnier,
Perceval Coudrain

Univ. Grenoble Alpes,
​CEA, France
​​

Environmental Assessment of the Fan-out Wafer Level Packaging Technology​​



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​ABOUT ESTC

The 11th IEEE Electronics System-Integration Technology Conference will be taking place in Helsinki from September 9-11, 2026. IEEE ESTC is the premier international event in the field of electronics packaging and system integration and the IEEE EPS flagship conference in Europe, co-sponsored by IMAPS Europe. This year’s conference is chaired by Toni Mattila from Business Finland.​

DL_Icon.pngMore information on ​ESTC​’s website


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Practical information

From 9/9/2026 to 9/11/2026Helsinki, Finland

Website​​​

 ContactJean-Charles Souriau  with any questions.​​


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CEA-Leti contacts

Jean-Charles Souriau

Research engineer in electronics







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