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3D integration: improving the precision and speed of direct hybrid bonding

CEA-Leti recently completed an equipment collaboration with SET (Smart Equipment Technology) for its direct hybrid bonding die-to-wafer process that combines precise alignment (under 1 micron) and high throughput. In collaboration with Intel, CEA-Leti is also exploring another die-to-wafer process that could multiply current production speeds by four.

Published on 24 November 2022

​The collaboration with SET focused on hybrid bonding between chips and wafers with copper and oxide surfaces. This scenario can be found for example in the case of AI chips that layer III-V materials (LED, image sensors...) on silicon components such as memory and CMOS circuits.

An industrial solution ready-to-go

The project led to the creation of a high throughput industrial production process that is precise to under one micron and is currently being used in CEA-Leti clean rooms.

The primary constraint was the need for an ultra-clean environment in order to guarantee that the bonded surfaces would be exempt from any contaminants. The equipment created in collaboration with SET meets this need thanks in particular to the adaptation of a robotics solution to avoid contamination. 

To improve throughput, researchers focused on how chips are cleaned after they are cut. They increased the speed of this costly step thanks to the development of an optimized cleaning strategy.

Collaboration with Intel: water droplets for improved production rates

Along similar lines, CEA-Leti is collaborating with Intel to explore another solution that might enable highly precise alignment thanks to the capillary forces of a water droplet. Many laboratories have been exploring this idea for years but without reaching industrial maturity.

The current solution being explored is to use a pick-and-place robot for imprecise, but rapid pre-alignment (more than 200 microns). The second step would be to finish the alignment process using the forces of capillarity in a water droplet, which is capable of aligning a die-to-wafer at 400nm.

This solution is only in an exploratory phase and requires the development of specific equipment. Several key points must be validated such as the compatibility of copper and water. However, the precision of alignment achieved via this solution would meet the demands of future generation circuits (500nm). The use of a fast pick-and-place robot would open the way for a production rate of 2,000 chips per hour,  more than four times faster than current industrial production speeds.

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