CMOS technology is based on two types of transistors: PMOS and NMOS. These devices perform complementary functions: when one conducts current, the other blocks it, and vice versa. Together, they form the logic elements used to perform computations or control power devices.
Traditionally, these silicon-based logic elements are fabricated on a separate chip from the power device. However, by using a material such as gallium nitride (GaN), both functions can be integrated onto a single chip, helping reduce the overall size of the resulting devices.
"Until now, the scientific literature has described solutions for fabricating GaN PMOS transistors, but they have remained relatively large," explains Julien Buckley, Research Engineer specializing in GaN power devices at CEA-Leti. "We therefore proposed studying an approach that could further reduce the size of these logic elements."
Numerical Simulations of Multiple PMOS Transistor Designs
This work was carried out within the Carnot ePMOS project, where the "e" refers to an innovative approach based on using electrons to conduct current within the PMOS transistor.
"The Carnot program gave us the opportunity to conduct exploratory research on a technology that is still at an early stage of maturity," says Julien Buckley. "It was exactly the right framework for this work and enabled us to deepen our understanding of a technology we had already been investigating for several years."
The research team built on previous work - which resulted in a patent - describing a GaN PMOS architecture based on electron conduction. This approach already offered a significant reduction in transistor size.
The researchers then conducted detailed numerical simulations of the device.
"We evaluated several design options by varying different parameters," explains Julien Buckley. "For example, the transistor includes an aluminum gallium nitride (AlGaN) layer. We investigated the impact of aluminum concentration in the alloy, the layer thickness, and the addition of small amounts of magnesium."
These simulations identified the parameter combinations delivering the best performance, namely the highest current in the ON state and the lowest leakage current in the OFF state. The results were published in a scientific journal.
Experimental Work on the PMOS Contact Technology
In parallel, the ePMOS team conducted experimental work on one of the transistor's key technological building blocks: the electrical contact.
The researchers fabricated several contact structures while varying different parameters, including the thickness and composition of an indium gallium nitride (InGaN) layer.
Each version was then electrically characterized to determine the contact properties and identify the optimal parameters.
"It is also worth noting that we did not use gold for the contacts, but rather titanium nitride (TiN)," adds Julien Buckley. "This is particularly important for industrial applications, since gold is considered a contaminant in semiconductor manufacturing."
These experimental results were also published in a scientific journal.
Toward Smaller Power Converters
The researchers now plan to build and test the complete PMOS transistor based on the simulation results.
Once fully developed, the device could be used to manufacture more compact power converters, helping reduce the size of chargers for laptops, smartphones, and electric vehicles.
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