Stéphane Nicolas has been fostering his vocation, the development of sensors, since the mid-90s. After completing a PhD in this field, he joined the industry, where he focused on developing new MEMS sensors, especially accelerometers and gyrometers. In 2009, after six years with Tronics Microsystems, a CEA-Leti startup, he joined this leading research center.
For about a decade, he focused on refining integration and packaging methods for MEMS sensors, before turning his expertise towards image sensors, a category of components that is ubiquitous in smartphones. In particular, he helped develop PIXCURVE technology, which improves performance while simplifying optical architectures.
Complementary technologies: hybrid bonding and HD-TSV
Since 2022, Stéphane has been a project leader in 3D integration. As part of the 
Smart Imager program at the Nanoelec IRT (Technological Research Institute), and in collaboration with industrial partners (STMicroelectronics, Prophesee, Lynred, SIEMENS) and research laboratory G-InP, his research has contributed in developing a new generation of image sensors.
“Simply put, CMOS image sensors are made up of two layers: one contains photodiodes that detect photons, and the other collects and processes signals produced by the photodiodes," he described. “Our aim is to add a third layer, which will integrate AI in order to process the data that is produced by these images within the sensor itself."
However, adding another layer introduces technical challenges. “Currently, thanks to a direct bonding process called hybrid bonding, it is usual to bond the front side of two wafers, the one containing the active layers," Stéphane added. “But with a third layer, it becomes necessary to rely on connections through one of the wafer's back side, which is made of silicon." To do so, scientists have developed “Through-Silicon Via" (TSV) interconnections with high densities (HD). This involves reducing one of the silicon wafers to a thickness below 10 µm, creating vias through the remaining silicon thickness, and filling these holes with metal while ensuring electrical insulation from surrounding materials.
Then, it is possible to perform a second hybrid bonding step to connect the third wafer to the first two. However, this stage involves a serious challenge. “Hybrid bonding requires perfectly flat surfaces, with a very low topography and roughness," Stéphane explained.
“These requirements must be fulfilled once the TSVs have been produced, particularly during the critical polishing stage, otherwise the hybrid bonding interconnection will not be possible."
Getting closer to a three-layer image sensor demonstrator
The research paper written by Stéphane and his colleagues specifically addresses the development of a demonstrator that makes use of these complementary technologies. Through characterization tests, the research team demonstrated electrical continuity across all the demonstrator layers. Good electrical performances proved the success of this manufacturing method.
The next stage will be to develop a full three-layer CMOS image sensor demonstrator that integrates a neural network. Its performance will be checked using electrical and optical tests.
“We are aiming for first results by late 2027, after the conception, design, and manufacturing phases," Stéphane announced.