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Sequential 3D integration soon within reach

​Low-temperature (< 500 °C) transistor fabrication processes were implemented at CEA-Leti, a CEA Tech institute to demonstrate the integration of powerful CMOS systems in a world first. The successful implementation of these processes will pave the way toward sequential 3D integration that does not damage the chip or negatively impact performance.

Published on 24 September 2020

​Sequential 3D integration has emerged as a potential alternative to reducing size as a way to continue to increase the density of integrated circuits. CEA-Leti recently overcame one of the main hurdles to developing 3D integration. 3D integration involves stacking transistors vertically. The fabrication processes used for the transistors at the top of the stack involve high temperatures that damage the transistors at lower levels in the stack, reducing the performance of the entire chip.

In this world first, CEA-Leti researchers successfully lowered process temperatures under the critical threshold of 500 °C. To do so, they modified several key process steps. New materials selected specifically for deposition at lower temperatures were tested; the epitaxy processes were modified to be carried out at 500 °C instead of the usual 600 °C and 750 °C; and the solid-phase epitaxy regrowth (SPER) was utilized at 500 °C to activate the junction instead of the final annealing (generally at temperatures in excess of 1,000 °C). Last, but not least, a grid recrystallization process was developed to prevent deterioration of the lower-level transistors. 

The demonstration was completed on a planar structure, and the process must now be tested on a sequential 3D integrated device and the reliability of the grid must be further improved. The research was presented at the recent VLSI conference with Samsung. It will pave the way toward high-performance monolithic 3D CMOS integration for advanced logic, RF, imager, in-memory computing, and AI circuits.

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