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Press release | Focus
Invited paper at IEDM 2020 shows benefit of CEA-List's architectures in co-optimizing CEA-Leti's 3D toolbox to enable higher bandwidth & heterogeneity for high-performance processors.
Profound evolutions brought by high performance computing (HPC) applications are based on continuous and exponential increases in computing performances over the past decades, explained the paper, How 3D integration technologies enable advanced compute node for Exascale-level High Performance Computing?. Supercomputers will soon achieve exascale-level computing performances mainly thanks to the introduction of innovative hardware technologies around the processors.
These R&D successes open a path towards heterogeneous processors that
will enable exascale-level supercomputers,” said Denis Dutoit, a CEA-List
scientist and lead author of the IEDM paper. “We demonstrated that
co-optimization of advanced architectures with 3D integration technologies
achieves the level of computing performance and bandwidth required for HPC.
Current CEA-Leti research work addresses die-to-wafer direct hybrid-bonding technology, which offers denser 3D interconnects with better electrical, mechanical and thermal parameters, and allows ultrahigh-bandwidth capabilities in heterogeneous systems. CEA-Leti also is working on high-density through silicon vias (TSV) (pitch 1 to 4 µms) to create together with die-to-wafer hybrid bonding a complete dense 3D stack. For the longer term, CEA-Leti is also investigating innovative photonic-interposer technology as a 3D-based photonic chiplet approach to enable interconnection of tens of computing chiplets with the resulting chip-to-chip communication bandwidth, latency and energy.
CEA is a French government-funded technological research organisation in four main areas: low-carbon energies, defense and security, information technologies and health technologies. A prominent player in the European Research Area, it is involved in setting up collaborative projects with many partners around the world.