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CEA-LETI Develops Circuits for Neuromorphic Processors That Replace CMOS Transistor-Based Tcam Memory With Rram-Based Tcam Memory

​IEDM Paper Explains a Breakthrough on an Existing Structure that Reduces Silicon Area 8x Compared To 16-Transistor Ternary Content-Addressable Memories And Meets Performance and Reliability Requirements of Those Processors

Published on 5 December 2018

​SAN FRANCISCO – Dec. 5, 2018 – Leti, a research institute at CEA Tech, has proven that RRAM-based ternary-content addressable memory (TCAM) circuits, featuring the most compact structure developed to date, can meet the performance and reliability requirements of multicore neuromorphic processors.

TCAM circuits provide a way to search large data sets using masks that indicate ranges. These circuits are, therefore, ideal for complex routing and big data applications, where an exact match is rarely necessary.  TCAM circuits allow searching for stored information by its content, as opposed to classic memory systems in which a memory cell’s stored information is retrieved by its physical address. They shorten the search time compared to classic memory-based search algorithms, as all the stored information is compared with the searched data in parallel, within a single clock cycle. 

But conventional SRAM-based TCAM circuits are usually implemented with 16 CMOS transistors, which limits storage capacity of TCAMs to tens of Mbs in standard memory structures, and takes up valuable silicon real estate in neuromorphic computing spiking neural-network chips.

The breakthrough of the CEA-Leti project replaced SRAM cells with resistive-RAM (RRAM) in TCAM circuits to reduce the number of required transistors to two (2T), and to two RRAMs (2R), which is the most compact structure for these circuits produced to date. In addition, the RRAMs were fabricated on top of the transistors, which also consumed less area. This suggests such a 2T2R structure can decrease the required TCAM area by a factor of eight compared to the conventional 16-transistor TCAM structure.

But while using RRAMs in TCAM circuits significantly reduces both silicon chip area needed and power consumption, and guarantees similar search speed compared to CMOS-based TCAM circuits, this approach brings new challenges:

  • Circuit reliability is strongly dependent on the ratio between the ON and OFF states of the memory cells. RRAM-based TCAM reliability could be affected by the relatively low ON/OFF ratio (~10-100) with respect to the 16-transistor structure (~105), and 
  • RRAMs have a limited endurance with respect to CMOS transistors, which can affect the lifespan of the system.

Overcoming these challenges requires trade-offs:

  • The voltage applied during a search operation can be decreased, which improves system reliability. However, this also degrades system performance, e.g. slower searches, and
  • The limited endurance can be overcome by either decreasing the voltage applied during each search, or increasing the power used to program the TCAM cells beforehand. Both increase system endurance, while slowing searches.

The work, presented Dec. 4 at IEDM 2018 in a paper entitled, “In-depth Characterization of Resistive Memory-based Ternary Content Addressable Memories”, clarifies the link between RRAM electrical properties and TCAM performance with extensive characterizations of a fabricated RRAM-based circuit. 

The research showed a trade-off exists between TCAM performance (search speed) and TCAM reliability (match/mismatch detection and search/read endurance). This provides insights into programming RRAM-based TCAM circuits for other applications, such as network packets routing.

“Assuming many future neuromorphic computing architectures will have thousands of cores, the non-volatility feature of the proposed TCAM circuits will provide an additional crucial benefit, since users will have to upload all the configuration bits only the first time the network is configured,” said Denys R.B. Ly, a Ph.D. student at Leti and lead author of the paper. “Users will also be able to skip this potentially time-consuming process every time the chip is reset or power-cycled.”

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