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Leti To Present Update Of Coolcube/3dvlsi Technologies Development at 2017 IEEE S3S

Future Developments and Tape-Out Vehicles to Be Presented during Oct. 17 Workshop

Published on 12 October 2017

Leti, a research institute of CEA Tech, will hold a workshop on Oct. 17 to present updates on their progress developing CoolCubeTM high-density 3D sequential, monolithic-integration technology, and their supporting design-and-manufacturing ecosystems.

The workshop at the Hyatt Regency San Francisco Airport, Burlingame, Calif., is an official satellite event of the 2017 IEEE S3S conference. It will feature presentations from Leti and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, as well as partner firms, such as Applied Materials, SCREEN Semiconductor and HP Enterprise. Workshop attendees will include representatives of a growing ecosystem of design, manufacturing, and related companies.

As an extension of High Density 3D Cu-Cu/Hybrid Bonding Chip-to-Wafer/Wafer-to-Wafer Technologies, the CoolCubeTM  concept enables stacking active layers of transistors in the third dimension, while coping with thermal budgets that do not degrade the performance of transistors or metal interconnects. Leti and Qualcomm have been collaborating for four years on various 3DVLSI advanced concepts, which have broad applications in low-power mobile devices and other IC platforms.

Workshop topics will include:

  • a review of 3DVLSI research at Qualcomm Technologies
  • an update on Leti's technology and design
  • a complete Leti 3D-technologies landscape presentation, and
  • exploration of expectations and challenges around 3DVLSI technology.

The workshop is designed to encourage an active exchange of ideas among attendees on applications, markets, integration and other related areas.

Leti will highlight technological solutions available now for top-tier CMOS integration using CoolCubeTM:

  • high-quality mono-crystalline channel
  • high-performance source/drain contacts
  • high-reliability gate stack and
  • low-parasitic stable intermediate back-end-of-line on 300mm wafers.

Leti this year taped out a test vehicle based on its internal technology and CoolCubeTM circuit and will publish final results of the test in 2018. In this CMOS integration, the technology starts from 28nm foundry wafers and extends to current Leti top-tier processes. During the Oct. 17 workshop, Leti will present the next step: a new CoolCubeTM tape-out, scheduled for mid-2018 and open to partners and collaborators. It is targeted to demonstrate by hardware promising applications enabled by CoolCube™/3DVLSI.  Design contributions are already planned or expected in the following fields: neuromorphic, near-memory processing, high-performance FPGA and energy-efficient computing. 

"As CoolCubeTM has evolved, its development team has received a growing number of inquiries from companies and organizations all along the semiconductor value chain, including materials and equipment suppliers, electronic design automation (EDA) companies, fabless chipmakers and foundries, and assembly and test houses," said Jean-Eric Michallet, Leti Head of Microelectronics Components Department. "Mutual cooperation will be an essential element of successful integration into high-volume production, and representatives of companies in these sectors are encouraged to attend the workshop."

Oct. 17 CoolCube/3DVLSI Workshop: Registration is open, free and available to S3S attendees. Attendance is limited to registered guests. Contact

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