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Published on 7 December 2023
Research FieldComputer science and software

Domaine-SComputer science and software

ThemeEngineering sciences

Theme-SEngineering sciences

Computer science and software Engineering sciences Computer science and software Engineering sciences DRT DACLE SCSN LCE Saclay
Software and hardware combined acceleration solution for operations research algorithms
The purpose of the study is to prepare the next generation of OR solvers. We will study the hardware acceleration possibility based on FPGA to run some or all of the OR algorithm. The blocks for which such a solution is not effective can be parallelized and executed on a standard computing platform. Thus, the proposed runtime correspond to a standard computing platform integrating FPGA. To access to this platform we require a set of tools. These tools should provide features such as (a) analysis and pre-compiling an input or problem or sub-problem of OR, (b) HW / SW partitioning and dedicated logic optimization and finally (c) generating an software executable and a bitstream. The first step will be to find OR algorithms that are well suited for hardware acceleration. We then propose a HW / SW partitioning methodologies for different classes of algorithms. The results will be implemented to lead to a compilation prototype starting from an OR instance and generating a software executable and a bitstream. Theses results will be implemented and executed on a computing platform integrating FPGA to evaluate the performance gain and the impact on the energy consumption of the proposed solution.
Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Service Calcul et Systèmes Numériques Laboratoire Calcul Embarqué
TRABELSI Kods CEA DRT/DSCIN/LECA Institut Carnot CEA LIST Architecture & IC Design, Embedded Software Department Embedded Real Time System foundations Laboratory CEA Saclay- Nano-INNOV Bât 862 - PC 172 F91191 GIF-SUR-YVETTE CEDEX 0169080006
Start date1/1/2016

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