You are here : Home > PsD-DRT-17-0098



Published on 3 December 2023
Research FieldElectronics and microelectronics - Optoelectronics

Domaine-SMathematics - Numerical analysis - Simulation

ThemeEngineering sciences

Theme-SEngineering sciences

Electronics and microelectronics - Optoelectronics Engineering sciences Mathematics - Numerical analysis - Simulation Engineering sciences DRT DACLE SCSN LISAN Grenoble
Hardening energy efficient security features for the IoT in FDSOI 28nm technology
The security of the IoT connected objects must be energy efficient. But most of the work around hardening by design show an additional cost, a multiplying factor of 2 to 5, on the surface, performance, power and energy, which does not meet the constraints of the IoT. Last 5 years research efforts on hardening have been guided by reducing silicon area or power, which do not always imply a decrease in energy, predominant criterion in autonomous connected objects. The postdoc topic addresses the hardening and energy consumption optimization of the implementation of security functions (attack detection sensors, cryptographic accelerator, random number generator, etc.) in 28nm FDSOI technology. From the selection of existing security bricks, unhardened in FPGA technology, the postdoc will explore hardening solutions at each step of the design flow in order to propose and to validate, into a silicon demonstrator, the most energy efficient countermeasures that guarantee a targeted security level. To achieve those goals, the postdoc can rely on existing methodologies of design and of security evaluation thanks to test benches and attack tools.
Département Architectures Conception et Logiciels Embarqués (LIST-LETI) Service Calcul et Systèmes Numériques Laboratoire Intégration Silicium des Architectures Numériques
BACLES-MIN Simone CEA DRT/DACLE//LISAN Commissariat à l’énergie atomique et aux énergies alternatives MINATEC Campus 17 rue des Martyrs 38054 Grenoble Cedex 9 +334 38 78 58 39
Start date1/10/2017

Retour à la liste