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A Versatile Platform towards High Reliability Compact Package for Digital Chips

Published on 29 March 2018
A Versatile Platform towards High Reliability Compact Package for Digital Chips
Ferrandon C., Castagne L., Kholti B., Waltener G., Lemaire R., Puyal V., Souriau J.-C., Simon G., Peltier J.-P., Lacrevaz T., Toffanin L.
Source-TitleProceedings - Electronic Components and Technology Conference
Univ. Grenoble Alpes, Grenoble, France, CEA, LETI, MINATEC Campus, Grenoble, France, E2v Semiconductors, 4 rue Rocheplaine, Saint Egrève, France, Savoie Mont Blanc University, IMEP-LAHC Laboratory, Le Bourget du Lac, France, STmicroelectronics, 12 rue Jules Horowitz, Grenoble, France
A technological multi-chip module with a large silicon interposer has been designed, manufactured and characterized for space and airborne applications. It stands for a reconfigurable advanced calculation device, for up to 10 Gbps data rate. The electrical targets are propagation losses less than 2 dB at 5GHz for the signal path across the interposer and its bumps, signal integrity with enough eye diagram opening for 10 Gbps rate signal, and power integrity. The mechanical targets are thermal warpage management and easy handling and assembly of the interposer in order to build a reliable module. This demonstrator integrates three large top dies on a packaging platform constituted of a 700 mm2 mid-density passive silicon interposer, reported on a 45 × 45 mm2 ceramic substrate. The interposer design rests on four copper layers: the three last copper layers of B55 (C65-based) technology for the front side, and a thick 4 to 8 ?m copper redistribution layer technology for the backside. The through-silicon-via technology used is a via-last technology. At 5 GHz, this design achieves 0.22 dB/mm propagation loss on the front side, and 0.1 dB loss per TSV with high resistivity silicon substrate. Besides, the silicon interposer is deemed suitable for a 19 W processor die power supply, exhibiting 11 mV drop voltage between a backside bump and two front side bumps. After design and electrical studies, the manufacturing is presented from the interposer process steps to the assembly steps and characterized thanks to RF and DC test patterns. TSV's and the three types of bumps resistances are given. Focus is made on important topics for higher performances such as inter-die distance reduction or front side layers typology, and on important topics for high reliability such as the silicon interposer's warpage behavior or the under-filling process development under large dies. © 2017 IEEE.
Assembly, High reliability applications, Large silicon interposer, Mid-density computing, Power distribution, Signal integrity, SiP
Assembly, Busbars, Ceramic materials, Chip scale packages, Copper, Dies, Electric power systems, Electronics packaging, Integrated circuit manufacture, Network components, Reliability, Silicon, Substrates, System-in-package, High reliability, Mid-density computing, Power distributions, Signal Integrity, Silicon interposers, Three dimensional integrated circuits

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