You are here : Home > ITAC: A complete 3D integration test platform

Publications

ITAC: A complete 3D integration test platform

Published on 29 March 2018
ITAC: A complete 3D integration test platform
Description
 
Date 
Authors
Lattard D., Arnaud L., Garnier A., Bresson N., Bana F., Segaud R., Jouve A., Jacquinot H., Moreau S., Azizi-Mourier K., Chantre C., Vivet P., Pillonnet G., Casset F., Ponthenier F., Farcy A., Lhostis S., Michailos J., Arriordaz A., Cheramy S.
Year2017-0337
Source-Title2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
Affiliations
CEA, LETI, MINATEC Campus, 17 rue des Martyrs, Grenoble, France, STMicroelectronics, 850 rue Jean Monnet, Crolles, France, Mentor Graphics, Inovallée Montbonnot, St Ismier, France
Abstract
System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of 'Integrated Technological and Application Circuits' for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 ?m diameter 20 ?m pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test. © 2016 IEEE.
Author-Keywords
3D stacking, Cu-pillar, test platform
Index-Keywords
DC-DC converters, 3D stacking, 3D stacking technology, Application circuits, Cu pillar, High performance computing, High-performance computing applications, Technology development, Test platforms, Three dimensional integrated circuits
ISSN 
LinkLink

Retour à la liste