Overview of several applications of chemical downstream etching (CDE) for IC manufacturing: Advantages and drawbacks versus WET processes
| Description | |
| Date | |
| Authors | De Buttet C., Prevost E., Campo A., Garnier P., Zoll S., Vallier L., Cunge G., Maury P., Massin T., Chhun S. |
| Year | 2017-0057 |
| Source-Title | Proceedings of SPIE - The International Society for Optical Engineering |
| Affiliations | CEA, LETI, MINATEC Campus, 17 rue des Martyrs, Grenoble Cedex 9, France, STMicroelectronics, 850 rue Jean Monnet, Crolles Cedex, France, LTM CNRS/UJF, Minatec 17, avenue des Martyrs, Grenoble Cedex 9, France |
| Abstract | Today the IC manufacturing faces lots of problematics linked to the continuous down scaling of printed structures. Some of those issues are related to wet processing, which are often used in the IC manufacturing flow for wafer cleaning, material etching and surface preparation. In the current work we summarize the limitations for the next nodes of wet processing such as metallic contaminations, wafer charging, corrosion and pattern collapse. As a replacement, we promoted the isotropic chemical dry etching (CDE) which is supposed to fix all the above drawbacks. Etching steps of SI3N4 layers were evaluated in order to prove the interest of such technique. © 2017 SPIE. |
| Author-Keywords | CDE, Chemical downstream etching, CMOS, Si3N4 etching, Wet etching |
| Index-Keywords | CMOS integrated circuits, Dry etching, Integrated circuits, Manufacture, Shotcreting, Timing circuits, IC manufacturing, Metallic contamination, Pattern collapse, Printed structures, Surface preparation, Wafer charging, Wafer cleaning, Wet-processing, Wet etching |
| ISSN | 0277786X |
| Link | Link |