What it can do
CEA-Leti's 3D integration technologies respond to tomorrow’s challenges in a wide range of applications, including
high-performance computing (HPC), AI, co-package optics, RF integration, quantum computing, power delivery, and also imagers and displays.
For HPC and AI, for example, each chiplet can be optimized according to its function (processor, accelerator, memory, serializer/deserializer, etc.). The number of computing and memory chiplets can be increased as needed, and chiplets with other functions (RF communication, microcontrollers, power management, sensors, imagers, etc.) can also be integrated.
This project has received funding from the European Union and Chips JU (Prevail and Fames projects), supported by French public authorities (France 2030 in particular through IRT Nanoelec, IPCEI ME and NextGen project).
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What makes it unique
Heterogeneous 3D chiplet integration offers unprecedented flexibility.
Each chiplet, depending on its function and the requirements of the target application, can be optimized separately and manufactured using the most
appropriate technology node, resulting in the best possible PPACE tradeoff.
Substrates of different sizes and materials from different foundries can be
assembled with agressive interconnect pitches using standard semiconductor
industry processes.
CEA-Leti offers advanced hybrid bonding, with aggressive pitches, in different
flavors : wafer-to-wafer and die-to-wafer assembly, including capability of
handling Know-Good-Dies (KGD) to support industry test requirements, and with
different materials allowing heterogeneous integration (the widely used copper
but also Ti, GaN, InP, Nb, glass substrate, low temperature annealing, etc).
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