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The aim of the PICTURE project is to develop on-chip technology capable of generating light, encoding data at very high speed and emitting and collecting this light through optical fiber.

Published on 6 May 2021

High Performance and High Yield Heterogeneous III-V/Si Photonic Integrated Circuits using a Thin and UniformBonding Layer

The aim of the PICTURE project is to develop on-chip technology capable of generating light, encoding data at very high speed and emitting and collecting this light through optical fiber.


Starting date : Jan. 2018 > Dec. 2020

Lifetime: 36 months

Program in support :  H2020-ICT-2017-1 (Information and Communication Technologies)


Status project : complete

CEA-Leti's contact :

Karim Hassan

Laurent Fulbert

Project Coordinator: III-V Lab (FR)


  • BE: Imec
  • CZ: Argotech
  • FR: III-V Lab, CEA-Leti, Nokia
  • IE: Tyndall

Target market: n/a


  • «Gate Oxide Process for III-V / Si Hybrid MOS Capacitor
    Modulator», S. Malhouitre, V. Ramez, V. Muffato, Y. Desières,
    K. Hassan, Submitted to IEEE Group IV Photonics Conference,
    Singapore, 2019.

Investment:  € 4 m.

EC Contribution€ 3.9 m.



CEA-Leti contribution to the PICTURE project

  • Enhancement of its 200 mm silicon photonics platform by implementing a new III-V on-silicon hybrid bonding scheme using a thin oxide bonding layer to produce optimized hybrid active devices such as hybrid III-V on Si lasers. These offer improved power efficiency and thermal behavior, very efficient, low-power consumption, III-V on Si hybrid capacitive modulators and photodiodes.

  • Patterning, encapsulation and planarization of silicon photonics devices has been successfully optimized to obtain a high bonding yield in 20 mm on thin oxide (~20nm) as shown in the scanning acoustic microscope image, in which the black areas represent successfully bonded interfaces.

  • The newly developed planarization steps involve a sequence of chemical and mechanical polishing and thin oxide deposition optimized to ensure high uniformity and selectivity above the silicon on insulator waveguides.

  • Multi-die bonding technology was also developed to use expensive III-V material only where it is necessary for active devices and to use III-V epitaxial stacks based on QW or QD active layers separately optimized for the laser, the modulator and the photodetector.

    The entire fabrication process of III-V on Si photonic integrated circuits is expected to be demonstrated on CEA-Leti’s 200 mm CMOS platform by the end of the project to confirm industrial manufacturability. In addition, CEA-Leti’s know-how in designing efficient, low-voltage, low power consumption modulators has been implemented to co-design hybrid III-V on Si modulators with the project partners. Characterization of all the passive and active building blocks up to 67 GHz operation on its Automatic Prober stations is planned for when the first devices become available.


  • The PICTURE project is developing photonic integration technology by bonding multi-III-V-dies of different epitaxial stacks to SOI wafers with a thinner, uniform dielectric bonding layer. This heterogeneous integration platform is expected to give higher performance lasers and photo-detectors based on the optimized III-V dies. Moreover, the thinner bonding layer could lead to outstandingly performant MOSCAP III-V/Si modulators and to a new generation of wavelength tunable, distributed feedback lasers. The overall process including the SOI process, bonding, III-V and back-end process is being developed on a 200mm R&D CMOS line to give higher yield, smaller footprint and lower cost PICs. Two types of PICs with a total capacity of 400Gb/s are currently being developed and will soon be packaged and validated in system configuration. The PICTURE project is also developing direct growth of high-performance quantum dot lasers and selective area growth on bonded templates for the future generation of high-density PICs. The project is coordinated by III-V Lab and its partners include the University of Southampton, CEA, University College London, Imec, Tyndall, Argotech and Nokia Bell Labs. This consortium is highly complementary and embraces all the skills required to fulfill the project objectives: growth of semiconductor materials, silicon process and III-V process, PIC design and characterization, PIC prototyping and assessment in high-bit-rate digital communication systems. Beyond the consortium’s capacity to fulfill the project objectives, its partners have the potential to set up a comprehensive supply chain for future usage of project results either “in house” or by establishing suitable partnerships.


  • Photonic integration technology developed in the PICTURE project will allow mass production, high yield, small footprint and low cost for a new generation of PICs jointly exploiting the advantages of III-V and silicon materials. This technology will demonstrate short-reach WDM PIC, requiring high volume manufacturing and long-reach coherent PIC targeting a smaller market. The consortium is ready to supply PICTURE-based PICs to the market, therefore contributing to strengthen the Europe’s position as a market leader for the most advanced, chip level, integrated solutions.