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IONS4SET project

​Ion-irradiation-induced Si nanodot Self-Assembly for Hybrid SET-CMOS Technology. The aim of the IONS4SET project was to create single electron transistors for ultra-low power electronics so that the component using these optimized transistors delivers good performance at very low energy consumption. This type of transistor requires fabrication of nanopillars well beyond the state of the art, which implement a process compatible with the semiconductor industry (CMOS).

Published on 26 June 2020



Starting date : January 2016 - July 2020 

Lifetime : 54 months

Program in support :


Status project in progress

CEA-Leti's contact :                           



Project Coordinator : Helmholtz Zentrum Dresden Rossendorf (DE)


  • CEA-Leti
  • Fraunhofer Institute for Integrated Systems and Device Technology
  • Helmholtz Zentrum Dresden Rossendorf (HZDR)
  • Institute of Microelectronics Barcelona (CSIC)
  • Universty of Helsinki
  • Consiglio Nazionale delle Richerche 

Target marketUltra-low power electronics

Investment: € 4 m.

EC Contribution€ 4 m.



Number of patents: n/a


  • The aim of the IONS4SET project is to develop a framework for reliably producing SETs that operate at room temperature using a semiconductor industry process flow. The final goal was a hybrid SET/FET electrical demonstrator.

  • The SET was a 10 - 12 nm diameter Gate-All Around (GAA) nanopillar with a 6 nm embedded oxide layer (SiO2) layer. In this layer, a single 2 -3 nm diameter silicon quantum nanodot (ND) wasformed by Siion implantation. During an annealing step, this silicon underwent phase separation and self-assembled into the ND. The bottom of the nanopillar was contacted electrically using the top-Si of an SOI advanced substrate.

  • Using the 200 mm silicon platform, CEA-Leti patterned < 30 nm diameter nanopillars, while ensuring the deposition, implantation and annealing steps for integration reasons. 20 nm diameter, 70 nm high nanopillars were created by Electron Beam Direct Write (EBDW) and etched using a standard trilayer stack. We delivered wafers to the project partners for dicing, advanced characterization and electrical integration. Energy-Filtered Transmission Electron Microscopy (EFTEM) showed that the pillars were the right size and contained a single silicon ND in the embedded oxide.

Energy filtered TEM image (resonant on Si plasmon) of a Si/SiO2/Si nanopillar with a nanodot in the embedded oxide. 
© Courtesy of HZDR.

  • CEA-Leti also investigated Directed Self-Assembly (DSA) of Block CoPolymers (BCP) as lithography for forming nanopillars. The first method involved forming PMMA contacts using a DSA contact shrink approach based on a PS-b-PMMA BCP. Sequential infiltration synthesis (SIS) was performed: Atomic Layer Deposition (ALD) was used to replace the PMMA with alumina (Al2O3), thus forming a hard mask for pillar patterning. The second method involved a PS-b-PMMA block copolymer with an inverse matrix for forming hexagonally organised sub-20 nm PS cylinders using a trilayer stack.

  • Billions of tiny computers that can sense and communicate from anywhere are coming online, creating the Internet of Things (IoT). As the IoT continues to expand, more and more devices require batteries and plugs. Gartner states that there will be nearly 26 billion devices connected to the IoT by 2020. Together with improved batteries, advanced computation and communication must therefore be delivered at extremely low-power consumption. 

  • Single Electron Transistors (SETs) are extremely low-energy dissipation devices that are complementary with CMOS: the SET is champion of low-power consumption, while CMOS advantages, such as high speed, driving, etc., compensate perfectly for the SET's intrinsic drawbacks. Hybrid SET-CMOS architectures require unrivalled integration and high performance, while manufacturability remains a roadblock for the large-scale use of such architectures. To ensure room temperature (RT) operation, single dots with diameters < 5 nm need to be fabricated and precisely positioned between source and drain with tunnel distances of a few nm. However, a reliable CMOS compatible process for co-fabricating RT-SETs and FETs is not yet available. IONS4SET's SET nanopillar paved the way for fabricating low-energy devices operating at RT based on a newly developed bottom-up self-assembly process. 

  • Lithography cannot deliver the 1-3 nm feature sizes required for RT operation but IONS4SET provided:

  1.  Controlled self-assembly of single ~ 2 nm Si dots 
  2. Self-alignment of each nanodot with source and drain at ~ 2 nm tunnel distances

  • The Si nanodot fabrication process involved:
  1. Ion irradiation through thin (few tens of nm) Si pillars with an embedded SiO2 layer
  2. Thermal activation of self-assembly.

  • Dot self-assembly works for narrow pillars only, hence nanopillar fabrication was crucial for IONS4SET. Finally, a power saving hybrid SET/CMOS device with a vertical gate-all-around nanowire GAA-SET was fabricated.


  • The IoT demands ultra-low power electronics to improve battery life and lower carbon footprint. SETs promise to achieve those requirements because of the ultra-low current through such devices. The IONS4SET project combined fundamental physics of quantum devices and selfassembly with advanced 3D CMOS manufacturing at the 10 nm length scale. Industry interest was proven by external industry committee members GlobalFoundries, STMicroelectronics and X-Fab.

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